1472N/A * or visit www.oracle.com if you need additional information or have any
1879N/A#include "precompiled.hpp"
1879N/A#include "c1/c1_CFGPrinter.hpp"
1879N/A#include "c1/c1_CodeStubs.hpp"
1879N/A#include "c1/c1_Compilation.hpp"
1879N/A#include "c1/c1_FrameMap.hpp"
1879N/A#include "c1/c1_LIRGenerator.hpp"
1879N/A#include "c1/c1_LinearScan.hpp"
1879N/A#include "c1/c1_ValueStack.hpp"
1879N/A#include "utilities/bitMap.inline.hpp"
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "vmreg_x86.inline.hpp"
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "vmreg_sparc.inline.hpp"
1879N/A#ifdef TARGET_ARCH_zero
1879N/A# include "vmreg_zero.inline.hpp"
2073N/A#ifdef TARGET_ARCH_arm
2073N/A# include "vmreg_arm.inline.hpp"
2073N/A#ifdef TARGET_ARCH_ppc
2073N/A# include "vmreg_ppc.inline.hpp"
0N/A #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
0N/Astatic int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1};
0N/Astatic int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1};
0N/A , _has_fpu_registers(false)
0N/A , _max_spills(0)
1969N/A , _needs_full_resort(false)
0N/A assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
0N/A return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
0N/A return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
0N/A return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
0N/A if (double_word) {
0N/A _max_spills++;
0N/A _max_spills++;
0N/A case noDefinitionFound:
0N/A case oneDefinitionFound:
0N/A assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
0N/A assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
0N/A case noOptimization:
0N/A case oneDefinitionFound: {
0N/A case oneMoveInserted: {
0N/A case storeAtDefinition:
0N/A case startInMemory:
0N/A case noOptimization:
0N/A case noDefinitionFound:
0N/A assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
0N/A assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
0N/A assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
0N/A assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
0N/A assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
0N/A assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
0N/A for (i = 0; i < num_blocks; i++) {
0N/A for (i = 0; i < num_blocks; i++) {
0N/Avoid LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
0N/A assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
0N/A assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
0N/A assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
0N/A // Add uses of live locals from interpreter's point of view for proper debug information generation
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
0N/A TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
0N/A change_occurred = false;
0N/A change_occurred_in_block = false;
0N/A change_occurred = true;
0N/A change_occurred_in_block = true;
0N/A tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
0N/A tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
0N/A } while (change_occurred);
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
0N/A tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
0N/A for (int j = 0; j < num_blocks; j++) {
0N/A assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
0N/Avoid LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
0N/Avoid LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
0N/A bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
0N/A if (result_in_memory) {
0N/A // input operand must have a register instead of output operand (leads to better register allocation)
0N/A return shouldHaveRegister;
0N/A return mustHaveRegister;
0N/A bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
0N/A if (result_in_memory) {
0N/A return mustHaveRegister;
0N/A // input operand must have a register instead of output operand (leads to better register allocation)
0N/A return mustHaveRegister;
0N/A return shouldHaveRegister;
0N/A return shouldHaveRegister;
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
0N/A case lir_logic_and:
0N/A case lir_logic_or:
0N/A case lir_logic_xor:
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
0N/A return mustHaveRegister;
0N/A if (o->is_single_stack()) {
0N/A } else if (o->is_double_stack()) {
0N/A assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
0N/A int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
0N/A case lir_convert: {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
0N/A if (has_fpu_registers()) {
304N/A for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
0N/A for (int k = 0; k < num_caller_save_registers; k++) {
0N/A for (i = 0; i < interval_count(); i++) {
0N/A for (i = 0; i < interval_count(); i++) {
0N/Avoid LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
0N/A assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
0N/A assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1969N/A if (_needs_full_resort) {
1969N/A _needs_full_resort = false;
0N/A sorted_len++;
0N/A sorted_idx++;
1969N/A if (_needs_full_resort) {
1969N/A _needs_full_resort = false;
0N/A if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
0N/A create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
0N/A if (has_fpu_registers()) {
0N/A create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
0N/A create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
0N/A if (has_fpu_registers()) {
0N/AInterval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
0N/A return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
0N/A return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
0N/Avoid LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
304N/A for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
0N/A assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
0N/A if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
0N/Avoid LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
0N/A assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
0N/A// insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
0N/A for (i = 0; i < num_blocks; i++) {
0N/A if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
0N/A assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
0N/A assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
0N/A if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
0N/A for (i = 0; i < num_blocks; i++) {
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
0N/Avoid LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1969N/A _needs_full_resort = true;
304N/A for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
0N/A // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
0N/Avoid LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
0N/A Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
0N/A if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
0N/Avoid LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
304N/A for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
0N/A // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
0N/A resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
0N/A for (i = 0; i < num_blocks; i++) {
0N/A for (i = 0; i < num_blocks; i++) {
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
1736N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
1601N/A#ifdef __SOFTFP__
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
1601N/A#ifdef __SOFTFP__
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
0N/A "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
0N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
1601N/A#ifndef __SOFTFP__
0N/A assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
0N/A assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
0N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
0N/A LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
1601N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
1601N/A assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
1601N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
1601N/A LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
0N/A assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
0N/A if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
0N/A assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
0N/A assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
1739N/A if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
0N/A assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
0N/AOopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
0N/A for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
0N/A assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
0N/A assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
0N/A assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2742N/A set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
0N/A for (int i = 0; i < locks_count; i++) {
0N/Avoid LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
3863N/AConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
3863N/AConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
3863N/AConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
3863N/AConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
3863N/AConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
3863N/ALocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
0N/A _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
0N/Aint LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
0N/Aint LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
0N/A DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
1060N/A DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
0N/A assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2835N/A#ifndef __SOFTFP__
2835N/A#ifndef VM_LITTLE_ENDIAN
2835N/A if (! float_saved_as_double) {
0N/A if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
0N/A // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
0N/A assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2192N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
0N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
1601N/A assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
1601N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2192N/A#ifdef VM_LITTLE_ENDIAN
0N/Aint LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
0N/A assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
0N/A assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
0N/A // The operand must be live because debug information is considered when building the intervals
0N/A assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
1739N/AIRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
1739N/A caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
0N/A if (nof_locals > 0) {
1739N/A for(int i = 0; i < nof_locals; i++) {
1739N/A int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
1739N/A return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
1739N/A info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
1739N/A DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
0N/A if (!use_fpu_stack_allocation()) {
0N/A if (insert_point != j) {
0N/A insert_point++;
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A if (use_fpu_stack_allocation()) {
0N/A for (i = 0; i < interval_count(); i++) {
0N/A for (i = 0; i < block_count(); i++) {
0N/A tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
0N/A if (PrintCFGToFile) {
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
0N/A tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
0N/A tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
0N/A if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
0N/A tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
722N/A create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
0N/A for (int i = 0; i < block_count(); i++) {
722N/A check_live = false;
722N/A if (check_live) {
0N/A TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
0N/A for (int i = 0; i < num_blocks; i++) {
304N/A for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
0N/A assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
0N/A // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
0N/A IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
0N/A void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
0N/A void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
0N/A if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
0N/A for (int i = 0; i < state_size(); i++) {
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
0N/A for (int i = 0; i < state_size(); i++) {
0N/A saved_state_correct = false;
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
0N/A if (saved_state_correct) {
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
0N/A return copy_state;
0N/A tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
0N/A // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
0N/A _multiple_reads_allowed(false),
0N/A _register_blocked[i] = 0;
0N/A assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
0N/A if (!_multiple_reads_allowed) {
0N/A assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
0N/A BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
0N/A if (!_multiple_reads_allowed) {
0N/A assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
0N/A assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
0N/A assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
0N/A// check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
0N/A if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
0N/A if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
0N/A LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
0N/A if (!_multiple_reads_allowed) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
0N/A TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
0N/A processed_interval = true;
0N/A spill_candidate = i;
0N/A if (!processed_interval) {
0N/A if (spill_slot < 0) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
0N/A _multiple_reads_allowed = false;
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
0N/A assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
0N/A TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
0N/A if (has_mappings()) {
0N/A _split_children(0),
0N/A _insert_move_when_activated(false),
0N/A _split_parent = this;
0N/A _current_split_child = this;
0N/A assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
0N/A if (!search_split_child) {
0N/A return _register_hint;
0N/A if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
0N/A return _register_hint;
0N/A tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
0N/A assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
0N/A assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
0N/A assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
0N/A assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
0N/A assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
0N/A assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
0N/A// when an interval is split, a bi-directional link is established between the original interval
0N/A assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
0N/A assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
0N/A assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
0N/A assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
0N/A const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
0N/A out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
0N/A assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
0N/AIntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
0N/A assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
0N/A while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
0N/A bool range_has_changed = false;
0N/A range_has_changed = true;
0N/A range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
0N/A if (range_has_changed) {
0N/A assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
0N/A TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
0N/A if (activate_current()) {
0N/Avoid IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
0N/A default: ShouldNotReachHere(); \
0N/ALinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
0N/A if (!only_process_use_pos) {
0N/A assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
0N/Ainline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
0N/A if (!only_process_use_pos) {
0N/Ainline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
0N/A assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
0N/A set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
0N/A set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
0N/A assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
0N/Aint LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
0N/A assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
0N/A return optimal_split_pos;
0N/Aint LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
0N/A // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
0N/A } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
0N/A if (do_loop_optimization) {
0N/A int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
0N/A assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
0N/A optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
0N/A return optimal_split_pos;
0N/A assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
0N/A if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
0N/A // must calculate this before the actual split is performed and before split position is moved to odd op_id
0N/A bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
0N/A assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
0N/A assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
0N/A int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
0N/A assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
0N/A assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
0N/A assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
0N/A assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
0N/Avoid LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
0N/A int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
0N/A assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
0N/A assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
0N/A assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
0N/Aint LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
0N/A if (i == ignore_reg) {
0N/A if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
0N/A min_full_reg = i;
0N/A if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
0N/A max_partial_reg = i;
0N/A return min_full_reg;
0N/A *need_split = true;
0N/A return max_partial_reg;
0N/Aint LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
0N/A if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
0N/A min_full_reg = i;
0N/A if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
0N/A max_partial_reg = i;
0N/A return min_full_reg;
0N/A *need_split = true;
0N/A return max_partial_reg;
0N/A init_use_lists(true);
0N/A assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
0N/A // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
0N/A TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
0N/A TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
0N/A assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
0N/A bool need_split = false;
0N/A if (_adjacent_regs) {
0N/A if (need_split) {
0N/Aint LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
0N/A if (i == ignore_reg) {
0N/A if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
0N/A *need_split = true;
0N/Aint LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
0N/A *need_split = true;
0N/A TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
0N/A init_use_lists(false);
0N/A assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
0N/A bool need_split = false;
0N/A if (_adjacent_regs) {
0N/A reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
0N/A if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
0N/A assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
0N/A if (need_split) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
0N/A return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
0N/A if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
0N/A Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
0N/A Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
0N/A assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
0N/A assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
0N/A // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
0N/A assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
0N/A } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
0N/A assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
0N/A assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
0N/A if (decrement_index) {
0N/A if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
0N/A assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
0N/A assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
0N/A TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
0N/A remove_cur_instruction(i, true);
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
0N/A assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
0N/A assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
0N/A if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
0N/A if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
0N/A TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
0N/A insert_idx++;
0N/A remove_cur_instruction(i, false);
0N/Avoid ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
0N/A assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
0N/A if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
0N/A assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
0N/A assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
0N/A assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
0N/Avoid ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
0N/A assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
0N/A if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
0N/A pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
0N/A assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
0N/A assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
0N/A switch (counter_idx) {
0N/A if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
0N/A return counter_method;
0N/A return counter_block;
0N/A return counter_instruction;
0N/A return counter_move_total;
0N/A return invalid_counter;
0N/A for (int i = 0; i < number_of_counters; i++) {
0N/A _counters_sum[i] = 0;
0N/A for (int i = 0; i < number_of_counters; i++) {
0N/A for (int i = 0; i < number_of_counters; i++) {
0N/A if (_counters_max[i] >= 0) {
0N/A bool has_xhandlers = false;
0N/A has_xhandlers = true;
0N/A case lir_std_entry:
0N/A case lir_rtcall:
0N/A case lir_static_call:
0N/A case lir_optvirtual_call:
0N/A case lir_branch:
0N/A case lir_cond_float_branch: {
0N/A case lir_mul_strictfp:
0N/A case lir_div_strictfp:
0N/A case lir_logic_and:
0N/A case lir_logic_or:
0N/A case lir_logic_xor:
0N/A case lir_alloc_object:
0N/A case lir_monaddr:
0N/A case lir_null_check:
0N/A case lir_instanceof:
0N/A case lir_checkcast:
0N/A case lir_fpop_raw:
0N/A case lir_convert:
0N/A case lir_roundfp:
0N/A if (has_xhandlers) {
0N/Avoid LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
0N/A for (int i = 0; i < number_of_timers; i++) {
0N/A if (TimeEachLinearScan) {
0N/A for (int i = 0; i < number_of_timers; i++) {
0N/A if (TimeEachLinearScan) {
0N/A tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
0N/A if (TimeLinearScan) {
0N/A for (int i = 0; i < number_of_timers; i++) {
0N/A tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);