/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
// FORMS.CPP - Definitions for ADL Parser Forms Classes
#include "adlc.hpp"
//==============================Register Allocation============================
//------------------------------RegisterForm-----------------------------------
// Constructor
}
RegisterForm::~RegisterForm() {
}
// record a new register definition
}
// record a new register class
return regClass;
}
// record a new register class
return allocClass;
}
// Called after parsing the Register block. Record the register class
// for spill-slots/regs.
// Stack slots start at the next available even register number.
reg_class->_stack_or_reg = true;
}
// Provide iteration over all register definitions
// in the order used by the register allocator
_current_ac = NULL;
}
// Check if we need to get the next AllocClass
if ( _current_ac == NULL ) {
}
// At end of this allocation class, check the next
_current_ac = NULL;
return iter_RegDefs();
}
return reg_def;
}
// return the register definition with name 'regName'
return regDef;
}
// return the register class with name 'className'
return regClass;
}
// Check that register classes are compatible with chunks
bool valid = true;
// Verify Register Classes
// check that each register class contains registers from one chunk
// Check the chunk value for all registers in this class
} // end of RegClasses
// Verify that every register has been placed into an allocation class
}
if( num_register_zero > 1 ) {
"ERROR: More than one register has been assigned register-number 0.\n"
"Probably because a register has not been entered into an allocation class.\n");
}
return valid;
}
// Compute RegMask size
// Need at least this many words
// The array of Register Mask bits should be large enough to cover
// all the machine registers and all parameters that need to be passed
// on the stack (stack registers) up to some interesting limit. Methods
// that need more parameters will NOT be compiled. On Intel, the limit
// is something like 90+ parameters.
// Add a few (3 words == 96 bits) for incoming & outgoing arguments to calls.
// Round up to the next doubleword size.
}
}
const char *name;
}
}
}
}
//------------------------------RegDef-----------------------------------------
// Constructor
RegDef::RegDef(char *regname, char *callconv, char *c_conv, char * idealtype, char * encode, char * concrete)
_register_num(0) {
// Chunk and register mask are determined by the register number
// _register_num is set when registers are added to an allocation class
}
}
}
// Bit pattern used for generating machine code
return _register_encode;
}
// Register number used in machine-independent code
return _register_num;
}
}
}
//------------------------------RegClass---------------------------------------
// Construct a register class into which registers will be inserted
RegClass::RegClass(const char *classid) : _stack_or_reg(false), _classid(classid), _regDef(cmpstr,hashstr, Form::arena),
{
}
// record a register in this class
}
// Number of registers in class
}
}
}
}
return reg_def;
}
reset();
}
}
return first;;
}
// Collect all the registers in this register-word. One bit per register.
int word = 0;
const char *name;
}
if( stack_also ) {
// Now also collect stack bits
for( int i = 0; i < 32; i++ )
word |= (1 << i);
}
return word;
}
}
const char *name;
}
}
//------------------------------AllocClass-------------------------------------
}
// record a register in this class
// Add regDef to this allocation class
}
}
const char *name;
}
}
//==============================Frame Handling=================================
//------------------------------FrameForm--------------------------------------
_alignment = NULL;
_return_addr = NULL;
}
}
}
}
//==============================Scheduling=====================================
//------------------------------PipelineForm-----------------------------------
: _reslist ()
, _rescount (0)
, _maxcycleused (0)
, _stages ()
, _stagecnt (0)
, _classlist ()
, _classcnt (0)
, _noplist ()
, _nopcnt (0)
, _variableSizeInstrs (false)
, _branchHasDelaySlot (false)
, _maxInstrsPerBundle (0)
, _maxBundlesPerCycle (1)
, _instrUnitSize (0)
, _bundleUnitSize (0)
, _instrFetchUnitSize (0)
, _instrFetchUnits (0) {
}
PipelineForm::~PipelineForm() {
}
}
const char *res;
const char *stage;
const char *cls;
const char *nop;
int count = 0;
if (_variableSizeInstrs)
if (_instrUnitSize > 0)
else
else
if (_instrUnitSize > 0)
else if (_bundleUnitSize > 0)
else
if (_branchHasDelaySlot)
if (_maxInstrsPerBundle > 0)
if (_maxBundlesPerCycle > 0)
if (_instrFetchUnitSize > 0 && _instrFetchUnits)
}
//------------------------------ResourceForm-----------------------------------
}
ResourceForm::~ResourceForm() {
}
return (ResourceForm *)(this);
}
}
}
//------------------------------PipeClassOperandForm----------------------------------
}
if (_more_instrs > 0)
if (_more_instrs > 0)
}
//------------------------------PipeClassResourceForm----------------------------------
}
}
//------------------------------PipeClassForm----------------------------------
, _has_fixed_latency(0)
, _fixed_latency(0)
, _instruction_count(0)
, _has_multiple_bundles(false)
, _has_branch_delay_slot(false)
, _force_serialization(false)
, _may_have_no_code(false) {
}
PipeClassForm::~PipeClassForm() {
}
return (PipeClassForm *)(this);
}
}
if (_ident)
if (_has_fixed_latency)
if (_force_serialization)
if (_may_have_no_code)
}
//==============================Peephole Optimization==========================
//------------------------------Peephole---------------------------------------
}
}
// Append a peephole rule with the same root instruction
} else {
}
}
// Store the components of this peephole rule
}
if( _constraint == NULL ) {
} else {
}
}
}
// class Peephole accessor methods are in the declaration.
}
// Output the next entry
}
//------------------------------PeepMatch--------------------------------------
}
}
// Insert info into the match-rule
int input) {
}
// Access info about instructions in the peep-match rule
return _max_position;
}
}
// Iterate through all info on matched instructions
}
}
// 'true' if current position in iteration is a placeholder, not matched.
return _instrs.current_is_signal();
}
}
}
//------------------------------PeepConstraint---------------------------------
int right_inst, char* right_op)
PeepConstraint::~PeepConstraint() {
}
// Check if constraints use instruction at position
// Check local instruction constraints
if( _left_inst == position ) return true;
if( _right_inst == position ) return true;
// Check remaining constraints in list
}
// Add another constraint
} else {
}
}
// Access the next constraint in the list
return _next;
}
}
}
//------------------------------PeepReplace------------------------------------
}
PeepReplace::~PeepReplace() {
}
// Add contents of peepreplace
}
}
// Access contents of peepreplace
}
}
}
}
}