c1_LIRGenerator_sparc.cpp revision 928
844N/A * Copyright 2005-2009 Sun Microsystems, Inc. All Rights Reserved. 0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 0N/A * This code is free software; you can redistribute it and/or modify it 0N/A * under the terms of the GNU General Public License version 2 only, as 0N/A * published by the Free Software Foundation. 0N/A * This code is distributed in the hope that it will be useful, but WITHOUT 0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 0N/A * version 2 for more details (a copy is included in the LICENSE file that 0N/A * accompanied this code). 0N/A * You should have received a copy of the GNU General Public License version 0N/A * 2 along with this work; if not, write to the Free Software Foundation, 0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 0N/A * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 0N/A * CA 95054 USA or visit www.sun.com if you need additional information or 0N/A * have any questions. 0N/A#
include "incls/_precompiled.incl" 0N/A // byte loads use same registers as other loads 0N/A//-------------------------------------------------------------- 0N/A//-------------------------------------------------------------- 0N/A//--------- loading items into registers -------------------------------- 0N/A// SPARC cannot inline all constants 0N/A// only simm13 constants can be inlined 0N/A // accumulate fixed displacements 0N/A // apply the shift and accumulate the displacement 0N/A // index is illegal so replace it with the displacement loaded into a register 0N/A // at this point we either have base + index or base + displacement 0N/A//---------------------------------------------------------------------- 0N/A//---------------------------------------------------------------------- 0N/A // the CodeEmitInfo must be duplicated for each different 0N/A // LIR-instruction because spilling can occur anywhere between two 0N/A // instructions and so the debug information must be different 0N/A // emit array address setup early so it schedules better 0N/A // range_check also does the null check 342N/A // Needs GC write barriers. 0N/A // this CodeEmitInfo must not have the xhandlers because here the 0N/A // object is already locked (xhandlers expects object to be unlocked) 0N/A// _ineg, _lneg, _fneg, _dneg 0N/A// for _fadd, _fmul, _fsub, _fdiv, _frem 0N/A// _dadd, _dmul, _dsub, _ddiv, _drem 0N/A// for _ladd, _lmul, _lsub, _ldiv, _lrem 0N/A break;
// check if dividend is 0 is done elsewhere 0N/A break;
// check if dividend is 0 is done elsewhere 0N/A // order of arguments to runtime call is reversed. 0N/A// Returns if item is an int constant that can be represented by a simm13 0N/A// for: _iadd, _imul, _isub, _idiv, _irem 0N/A // missing test if instr is commutative and if we should swap 0N/A// _ishl, _lshl, _ishr, _lshr, _iushr, _lushr 0N/A // Long shift destroys count register 0N/A // the old backend doesn't support this 0N/A// _iand, _land, _ior, _lor, _ixor, _lxor 0N/A// _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg 0N/A // generate compare-and-swap and produce zero condition if swap occurs 0N/A // generate conditional move of boolean result 0N/A // Use temps to avoid kills 0N/A // get address of field 0N/A // generate conditional move of boolean result 819N/A // Precise card mark since could either be object or array 928N/A // Make all state_for calls early since they can emit code 0N/A // Note: spill caller save before setting the item 0N/A // load all values in callee_save_registers, as this makes the 0N/A // parameter passing to the fast case simpler 0N/A// _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f 0N/A // To convert an int to double, we need to load the 32-bit int 0N/A // from memory into a single precision floating point register 0N/A // (even numbered). Then the sparc fitod instruction takes care 0N/A // of the conversion. This is a bit ugly, but is the best way to 0N/A // get the int value in a single precision floating point register 0N/A // This instruction can be deoptimized in the slow path : use 0N/A // O0 as result register. 928N/A // Evaluate state_for early since it may emit code 928N/A // Evaluate state_for early since it may emit code. 0N/A // in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction 0N/A // and therefore provide the state before the parameters have been consumed 0N/A BAILOUT(
"encountered unloaded_ciobjarrayklass due to out of memory error");
928N/A // Evaluate state_for early since it may emit code. 0N/A // cannot re-use same xhandlers for multiple CodeEmitInfos, so 0N/A // This instruction can be deoptimized in the slow path : use 0N/A // O0 as result register. 0N/A // must do this before locking the destination register as an oop register, 0N/A // and before the obj is loaded (so x->obj()->item() is valid for creating a debug info location) 0N/A // ensure the result register is not the input register because the result is initialized before the patching safepoint 0N/A // for longs, only conditions "eql", "neq", "lss", "geq" are valid; 0N/A // mirror for other conditions 0N/A // inline int constants which are small enough to be immediate operands 0N/A // add safepoint before generating condition code so it can be recomputed 0N/A // increment backedge counter if needed 342N/A // _bs->c1_write_barrier_pre(this, LIR_OprFact::address(addr)); 0N/A // This address is precise