/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_FrameMap.hpp"
#include "c1/c1_Instruction.hpp"
#include "c1/c1_LIRAssembler.hpp"
#include "c1/c1_LIRGenerator.hpp"
#include "c1/c1_Runtime1.hpp"
#include "c1/c1_ValueStack.hpp"
#include "ci/ciArray.hpp"
#include "ci/ciObjArrayKlass.hpp"
#include "ci/ciTypeArrayKlass.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "vmreg_sparc.inline.hpp"
#ifdef ASSERT
#else
#endif
// byte loads use same registers as other loads
load_item();
}
if (!r->is_constant()) {
}
_result = r;
} else {
load_item();
}
}
//--------------------------------------------------------------
// LIRGenerator
//--------------------------------------------------------------
case addressTag:
}
return opr;
}
return reg;
}
return new_register(T_INT);
}
//--------- loading items into registers --------------------------------
// SPARC cannot inline all constants
} else {
return false;
}
}
// only simm13 constants can be inlined
} else {
}
}
}
return false;
}
return new_register(T_INT);
}
// accumulate fixed displacements
if (index->is_constant()) {
}
if (index->is_register()) {
// apply the shift and accumulate the displacement
if (shift > 0) {
}
if (disp != 0) {
} else {
}
disp = 0;
}
// index is illegal so replace it with the displacement loaded into a register
disp = 0;
}
// at this point we either have base + index or base + displacement
if (disp == 0) {
} else {
}
}
if (index_opr->is_constant()) {
} else {
} else {
}
}
} else {
#ifdef _LP64
}
#endif
if (shift > 0) {
} else {
}
}
if (needs_card_mark) {
} else {
}
}
LIR_Opr r;
r = LIR_OprFact::longConst(x);
r = LIR_OprFact::intConst(x);
} else {
}
return tmp;
}
return r;
}
}
}
void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
}
void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {
}
void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {
}
if (is_power_of_2(c + 1)) {
return true;
} else if (is_power_of_2(c - 1)) {
return true;
}
return false;
}
} else {
}
}
//----------------------------------------------------------------------
// visitor functions
//----------------------------------------------------------------------
bool needs_range_check = true;
x->should_profile());
if (use_length) {
if (needs_range_check) {
}
}
if (needs_store_check) {
} else {
}
set_no_result(x);
// the CodeEmitInfo must be duplicated for each different
// LIR-instruction because spilling can occur anywhere between two
// instructions and so the debug information must be different
if (x->needs_null_check()) {
}
// emit array address setup early so it schedules better
LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);
if (GenerateRangeChecks && needs_range_check) {
if (use_length) {
} else {
// range_check also does the null check
}
}
if (GenerateArrayStoreCheck && needs_store_check) {
__ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info, x->profiled_method(), x->profiled_bci());
}
if (obj_store) {
// Needs GC write barriers.
}
if (obj_store) {
// Precise card mark
}
}
set_no_result(x);
if (x->needs_null_check()) {
info_for_exception = state_for(x);
}
// this CodeEmitInfo must not have the xhandlers because here the
// object is already locked (xhandlers expects object to be unlocked)
}
set_no_result(x);
}
// _ineg, _lneg, _fneg, _dneg
}
// for _fadd, _fmul, _fsub, _fdiv, _frem
// _dadd, _dmul, _dsub, _ddiv, _drem
switch (x->op()) {
rlock_result(x);
}
break;
switch (x->op()) {
break;
break;
default:
}
set_result(x, result);
}
break;
default: ShouldNotReachHere();
}
}
// for _ladd, _lmul, _lsub, _ldiv, _lrem
switch (x->op()) {
}
switch (x->op()) {
break; // check if dividend is 0 is done elsewhere
break; // check if dividend is 0 is done elsewhere
break;
default:
}
// order of arguments to runtime call is reversed.
set_result(x, result);
break;
}
rlock_result(x);
break;
}
default: ShouldNotReachHere();
}
}
// Returns if item is an int constant that can be represented by a simm13
} else {
return false;
}
}
// for: _iadd, _imul, _isub, _idiv, _irem
// missing test if instr is commutative and if we should swap
rlock_result(x);
if (is_div_rem) {
}
} else {
}
}
switch (tag) {
case floatTag:
case doubleTag: do_ArithmeticOp_FPU(x); return;
case longTag: do_ArithmeticOp_Long(x); return;
case intTag: do_ArithmeticOp_Int(x); return;
}
}
// _ishl, _lshl, _ishr, _lshr, _iushr, _lushr
// Long shift destroys count register
}
// the old backend doesn't support this
} else {
}
}
// _iand, _land, _ior, _lor, _ixor, _lxor
}
// _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg
if (x->x()->type()->is_float_kind()) {
__ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl));
} else {
}
}
// Use temps to avoid kills
// get address of field
}
if (type == objectType)
else {
}
// generate conditional move of boolean result
// Precise card mark since could either be object or array
}
}
switch (x->id()) {
case vmIntrinsics::_dabs:
case vmIntrinsics::_dsqrt: {
switch (x->id()) {
case vmIntrinsics::_dsqrt: {
break;
}
case vmIntrinsics::_dabs: {
break;
}
}
break;
}
case vmIntrinsics::_dexp: {
switch (x->id()) {
case vmIntrinsics::_dsin:
break;
case vmIntrinsics::_dcos:
break;
case vmIntrinsics::_dtan:
break;
case vmIntrinsics::_dlog:
break;
case vmIntrinsics::_dlog10:
break;
case vmIntrinsics::_dexp:
break;
default:
}
set_result(x, result);
break;
}
case vmIntrinsics::_dpow: {
LIR_Opr result = call_runtime(x->argument_at(0), x->argument_at(1), runtime_entry, x->type(), NULL);
set_result(x, result);
break;
}
}
}
// Make all state_for calls early since they can emit code
// Note: spill caller save before setting the item
// load all values in callee_save_registers, as this makes the
// parameter passing to the fast case simpler
int flags;
set_no_result(x);
}
// _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
// _i2b, _i2c, _i2s
switch (x->op()) {
switch (x->op()) {
break;
break;
break;
break;
break;
default:
}
set_result(x, result);
break;
}
// To convert an int to double, we need to load the 32-bit int
// from memory into a single precision floating point register
// (even numbered). Then the sparc fitod instruction takes care
// of the conversion. This is a bit ugly, but is the best way to
// get the int value in a single precision floating point register
break;
}
break;
}
break;
}
break;
default: ShouldNotReachHere();
}
}
// This instruction can be deoptimized in the slow path : use
// O0 as result register.
#ifndef PRODUCT
}
#endif
}
// Evaluate state_for early since it may emit code
}
// Evaluate state_for early since it may emit code.
// in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction
// and therefore provide the state before the parameters have been consumed
}
BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
}
}
while (i-- > 0) {
}
// Evaluate state_for early since it may emit code.
// Cannot re-use same xhandlers for multiple CodeEmitInfos, so
// clone all handlers (NOTE: Usually this is handled transparently
// by the CodeEmitInfo cloning logic in CodeStub constructors but
// is done explicitly here because a stub isn't being used).
}
while (i-- > 0) {
i * sizeof(jint)));
}
// This instruction can be deoptimized in the slow path : use
// O0 as result register.
varargs);
}
}
// must do this before locking the destination register as an oop register,
// and before the obj is loaded (so x->obj()->item() is valid for creating a debug info location)
}
if (x->is_incompatible_class_change_check()) {
stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception);
} else {
stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception);
}
x->profiled_method(), x->profiled_bci());
}
}
// ensure the result register is not the input register because the result is initialized before the patching safepoint
x->direct_compare(), patching_info,
x->profiled_method(), x->profiled_bci());
}
// for longs, only conditions "eql", "neq", "lss", "geq" are valid;
// mirror for other conditions
// swap inputs
}
}
// inline int constants which are small enough to be immediate operands
// inline long zero
} else if (tag == objectTag && yin->is_constant() && (yin->get_jobject_constant()->is_null_object())) {
} else {
}
set_no_result(x);
// add safepoint before generating condition code so it can be recomputed
if (x->is_safepoint()) {
// increment backedge counter if needed
}
// Generate branch profiling. Profiling code doesn't kill flags.
profile_branch(x, cond);
move_to_phi(x->state());
if (x->x()->type()->is_float_kind()) {
} else {
}
}
}
}
CodeEmitInfo* info) {
#ifdef _LP64
#else
#endif
}
CodeEmitInfo* info) {
#ifdef _LP64
#else
#endif
}
#ifndef _LP64
} else
#endif
{
}
} else {
}
if (is_obj) {
// _bs->c1_write_barrier_pre(this, LIR_OprFact::address(addr));
}
if (is_obj) {
// This address is precise
}
}
}
#ifndef _LP64
} else
#endif
{
}
}
}
assert (!x->is_add() && (type == T_INT || (is_obj LP64_ONLY(&& UseCompressedOops))), "unexpected type");
if (offset->is_constant()) {
#ifdef _LP64
#else
#endif
} else {
}
if (is_obj) {
// Do the pre-write barrier, if any.
// barriers on sparc don't work with a base + index address
ptr = new_pointer_register();
}
if (is_obj) {
// Seems to be a precise address
}
}