/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NIAGARAREGS_H
#define _SYS_NIAGARAREGS_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Niagara SPARC Performance Instrumentation Counter
*/
/*
* Niagara SPARC Performance Control Register
*/
#define CPC_PCR_PRIVPIC 0
#define CPC_PCR_PIC1_SHIFT 0
/*
* Niagara DRAM performance counters
*/
/*
* Niagara JBUS performance counters
*/
/*
* JBUS performance counters
*/
/*
* Hypervisor FAST_TRAP API function numbers for Niagara MMU statistics
*/
/*
* and HV_NIAGARA_SETPERF
*/
#ifndef _ASM
/*
* Niagara MMU statistics data structure
*/
typedef struct niagara_tsbinfo {
typedef struct niagara_mmustat {
/*
* performance counters
*/
#endif /* _ASM */
/*
* Bits defined in L2 Error Status Register
*
* (Niagara 1)
* +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
* |MEU|MEC|RW |RSV|MODA|VCID|LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
* +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
* 63 62 61 60 59 58-54 53 52 51 50 49 48 47 46
*
* (Niagara 2)
* +---+---+---+----+--------+----+----+----+----+----+----+----+----+
* |MEU|MEC|RW |MODA| VCID |LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
* +---+---+---+----+--------+----+----+----+----+----+----+----+----+
* 63 62 61 60 59-54 53 52 51 50 49 48 47 46
*
* (Niagara 1)
* +---+---+---+---+---+---+---+---+---+---+---+-------+------+
* |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU| RSVD1 | SYND |
* +---+---+---+---+---+---+---+---+---+---+---+-------+------+
* 45 44 43 42 41 40 39 38 37 36 35 34-32 31-0
*
* (Niagara 2)
* +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
* |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU|LVC|RSVD| SYND|
* +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
* 45 44 43 42 41 40 39 38 37 36 35 34 33-28 27-0
*
* Note that relative to error status bits, Niagara-1 is a strict subset of
* Niagara-2.
*/
/*
* These L2 bit masks are used to determine if another bit of higher priority
* is set. This tells us whether the reported syndrome and address are valid
* for this ereport. If the error in hand is Pn, use Pn-1 to bitwise & with
* the l2-afsr value. If result is 0, then this ereport's afsr is valid.
*/
/*
* Bits defined in DRAM Error Status Register (Niagara-2)
* Niagara-1 is strict subset
*
* +---+---+---+---+---+---+---+---+---+---+----------+------+
* |MEU|MEC|DAC|DAU|DSC|DSU|DBU|MEB|FBU|FBR| RESERVED | SYND |
* +---+---+---+---+---+---+---+---+---+---+----------+------+
* 63 62 61 60 59 58 57 56 55 54 53-16 15-0
*
*/
/* Bit mask for DRAM priority determination */
/*
* The following is the syndrome value placed in memory
* when an uncorrectable error is written back from L2 cache.
*/
/*
* This L2 poison syndrome is placed on 4 byte checkwords of L2
* when a UE is loaded or DMA'ed into L2
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NIAGARAREGS_H */