niagara2.c revision c6fc6a368e072b6deb37b62fe3f9895efc5316d1
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * CDDL HEADER START
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The contents of this file are subject to the terms of the
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Common Development and Distribution License (the "License").
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * You may not use this file except in compliance with the License.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * See the License for the specific language governing permissions
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * and limitations under the License.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * When distributing Covered Code, include this CDDL HEADER in each
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * If applicable, add the following below this CDDL HEADER, with the
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * fields enclosed by brackets "[]" replaced with your own identifying
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * information: Portions Copyright [yyyy] [name of copyright owner]
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * CDDL HEADER END
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Use is subject to license terms.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Hypervisor services information for the NIAGARA2 and Victoria Falls
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * CPU module
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterstatic uint64_t cpu_sup_minor; /* Supported minor number */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster HSVC_REV_1, NULL, HSVC_GROUP_VFALLS_CPU, VFALLS_HSVC_MAJOR,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster HSVC_REV_1, NULL, HSVC_GROUP_KT_CPU, KT_HSVC_MAJOR,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Negotiate the API version for Niagara2 specific hypervisor
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster status = hsvc_register(&cpu_hsvc, &cpu_sup_minor);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services "
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cpu_hsvc.hsvc_major, cpu_hsvc.hsvc_minor, status);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The setup common to all CPU modules is done in cpu_setup_common
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Initialize the cpu_hwcap_flags for N2 and VF if it is not already
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * set in cpu_setup_common() by the hwcap MD info. Note that this MD
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * info may not be available for N2/VF.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * This should not happen since hwcap MD info is always
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * available for KT platforms.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster ASSERT(cpu_hwcap_flags != 0); /* panic in DEBUG mode */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cpu_hwcap_flags |= AV_SPARC_VIS3 | AV_SPARC_HPC | AV_SPARC_FMAF;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster#endif /* KT_IMPL */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cpu_hwcap_flags |= AV_SPARC_VIS | AV_SPARC_VIS2 |
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster " does not have required sun4v page sizes"
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster " 8K, 64K and 4M: MD mask is 0x%x",
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Niagara2 supports a 48-bit subset of the full 64-bit virtual
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * address space. Virtual addresses between 0x0000800000000000
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * and must never be mapped. In addition, software must not use
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * pages within 4GB of the VA hole as instruction pages to
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * avoid problems with prefetching into the VA hole.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32));
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32));
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Niagara2 has a performance counter overflow interrupt
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Enable 4M pages for OOB.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Use CPU Makefile specific compile time define (if exists)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * to add to the contig preallocation size.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster contig_mem_prealloc_base_size = MB(SUN4V_CONTIG_MEM_PREALLOC_SIZE_MB);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Set the magic constants of the implementation.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The Cache node is optional in MD. Therefore in case "Cache"
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * node does not exists in MD, set the default L2 cache associativity,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * size, linesize.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The cpu_ipipe and cpu_fpu fields are initialized based on
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * the execution unit sharing information from the MD. They
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * default to the CPU id in the absence of such information.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Niagara 2 defines the core to be at the FPU level
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The cpu_chip field is initialized based on the information
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * in the MD and assume that all cpus within a chip
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * share the same L2 cache. If no such info is available, we
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * set the cpu to belong to the defacto chip 0.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster cp->cpu_m.cpu_chip = cpunodes[cp->cpu_id].l2_cache_mapping;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if (cp->cpu_m.cpu_chip == NO_L2_CACHE_MAPPING_FOUND)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster extern void niagara_kstat_init(void);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if ((cpucnt++ == 0) && (cpu_hsvc_available == B_TRUE))
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster extern void niagara_kstat_fini(void);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if ((--cpucnt == 0) && (cpu_hsvc_available == B_TRUE))
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * On Niagara2, any flush will cause all preceding stores to be
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * synchronized wrt the i$, regardless of address or ASI. In fact,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * the address is ignored, so we always flush address 0.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Trapstat support for Niagara2 processor
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The Niagara2 provides HWTW support for TSB lookup and with HWTW
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * enabled no TSB hit information will be available. Therefore setting
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * the time spent in TLB miss handler for TSB hits to 0.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fostercpu_trapstat_data(void *buf, uint_t tstat_pgszs)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Page coloring support for hashed cache index mode
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Node id bits from machine description (MD). Node id distinguishes
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * local versus remote memory. Because of MPO, page allocation does
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * not cross node boundaries. Therefore, remove the node id bits from
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * the color, since they are fixed. Either bit 30, or 31:30 in
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Victoria Falls processors.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * The number of node id bits is always 0 in Niagara2.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fostertypedef struct n2color {
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster uchar_t lomask; /* mask for bits below node id */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster uchar_t lobits; /* number of bits below node id */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Remove node id bits from color bits 32:28.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * This will reduce the number of colors.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * No change if number of node bits is zero.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster color = ((color >> m.nnbits) & ~m.lomask) | (color & m.lomask);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster ASSERT((color & ~(hw_page_array[szc].hp_colors - 1)) == 0);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Restore node id bits into page color.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * This will increase the number of colors to match N2.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * No change if number of node bits is zero.
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fostern2_color2hash(uint_t color, uchar_t szc, uint_t node)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster color = ((color & ~m.lomask) << m.nnbits) | (color & m.lomask);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster/* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * iterator NULL means pfn is VA, do not adjust ra_to_pa
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * iterator (-1) means pfn is RA, need to convert to PA
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * iterator non-null means pfn is RA, use ra_to_pa
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_pfn_2_color_cpu(pfn_t pfn, uchar_t szc, void *cookie)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_papfn_2_color_cpu(pfn_t papfn, uchar_t szc)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f};
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_get_nsz_color_cpu(uchar_t szc, uint_t color)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_get_color_shift_cpu(uchar_t szc, uchar_t nszc)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_convert_color_cpu(uint_t ncolor, uchar_t szc, uchar_t nszc)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster color = ncolor << (nhbits[szc] - nhbits[nszc]);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster (((pfn) & it->mi_mnode_pfn_mask) >> it->mi_mnode_pfn_shift)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Fosterpage_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color,
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster uint_t ceq_mask, uint_t color_mask, void *cookie)
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* convert RA to PA for accurate color calculation */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* first call after it, so cache these values */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster n2_color2hash(ceq_mask, szc, it->mi_mnode_mask);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster n2_color2hash(ceq_mask, szc, it->mi_mnode_mask));
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* restart here when we switch memblocks */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster if ((((page_papfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) &&
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* we start from the page with correct color and mnode */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* page color is PA[32:28] */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster /* page color is PA[32:28].PA[19:19] */
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * Preserve mnode bits in case they are not part of the
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * color mask (eg., 8GB interleave, mnode bits 34:33).
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * We deal 64K or 8K page. Check if we could the
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster * satisfy the request without changing PA[32:28]
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2);
a688bcbb4bcff5398fdd29b86f83450257dc0df4Allan Foster npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
goto done;
goto done;
goto done;
ceq_mask) == 0) {
mask);
goto done;
done:
return (pfn);
goto next_mem_block;
return (npfn);
n2color_t m;
for (i = 0; i < max_mem_nodes; i++) {
for (i = 0; i < mmu_page_sizes; i++) {
(void) memset(&m, 0, sizeof (m));
if (lo > 0) {
n2color[i] = m;
for (i = 0; i < MMU_PAGE_SIZES; i++) {
while ((colors >> a) == 0)
if (a <= nequiv_shades_log2[i]) {
colorequivszc[i] =