/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#include <sys/archsystm.h>
#include <sys/machparam.h>
#include <sys/machsystm.h>
#include <sys/elf_SPARC.h>
#include <vm/hat_sfmmu.h>
#include <sys/dditypes.h>
#include <sys/cpu_module.h>
#include <sys/prom_debug.h>
#include <sys/prom_plat.h>
#include <sys/sysmacros.h>
#include <sys/machtrap.h>
#include <sys/simulate.h>
#include <sys/niagara2regs.h>
#include <sys/trapstat.h>
#include <sys/mutex_impl.h>
#if defined(NIAGARA2_IMPL)
#elif defined(VFALLS_IMPL)
#endif
/*
* Hypervisor services information for the NIAGARA2 and Victoria Falls
* CPU module
*/
#if defined(NIAGARA2_IMPL)
};
#elif defined(VFALLS_IMPL)
};
};
#endif
void
cpu_setup(void)
{
extern int mmu_exported_pagesize_mask;
extern int cpc_has_overflow_intr;
extern size_t contig_mem_prealloc_base_size;
int status;
/*
* Negotiate the API version for Niagara2 specific hypervisor
* services.
*/
if (status != 0) {
"group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
}
/*
* The setup common to all CPU modules is done in cpu_setup_common
* routine.
*/
/*
* Initialize the cpu_hwcap_flags for N2 and VF if it is not already
* set in cpu_setup_common() by the hwcap MD info. Note that this MD
*/
if (cpu_hwcap_flags == 0) {
#ifdef KT_IMPL
/*
* This should not happen since hwcap MD info is always
* available for KT platforms.
*/
#endif /* KT_IMPL */
}
if ((mmu_exported_pagesize_mask &
" does not have required sun4v page sizes"
" 8K, 64K and 4M: MD mask is 0x%x",
/*
* Niagara2 supports a 48-bit subset of the full 64-bit virtual
* address space. Virtual addresses between 0x0000800000000000
* and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
* and must never be mapped. In addition, software must not use
* pages within 4GB of the VA hole as instruction pages to
* avoid problems with prefetching into the VA hole.
*/
/*
* Niagara2 has a performance counter overflow interrupt
*/
/*
* Enable 4M pages for OOB.
*/
/*
* Use CPU Makefile specific compile time define (if exists)
* to add to the contig preallocation size.
*/
#endif
}
/*
* Set the magic constants of the implementation.
*/
void
{
/*
* The Cache node is optional in MD. Therefore in case "Cache"
* node does not exists in MD, set the default L2 cache associativity,
* size, linesize.
*/
if (cpunode->ecache_size == 0)
if (cpunode->ecache_linesize == 0)
if (cpunode->ecache_associativity == 0)
}
void
{
/*
* The cpu_ipipe and cpu_fpu fields are initialized based on
* the execution unit sharing information from the MD. They
* default to the CPU id in the absence of such information.
*/
/*
* Niagara 2 defines the core to be at the FPU level
*/
/*
* The cpu_chip field is initialized based on the information
* in the MD and assume that all cpus within a chip
* share the same L2 cache. If no such info is available, we
* set the cpu to belong to the defacto chip 0.
*/
}
static int cpucnt;
void
{
extern void niagara_kstat_init(void);
(void) niagara_kstat_init();
}
/*ARGSUSED*/
void
{
extern void niagara_kstat_fini(void);
(void) niagara_kstat_fini();
}
/*
* On Niagara2, any flush will cause all preceding stores to be
* synchronized wrt the i$, regardless of address or ASI. In fact,
* the address is ignored, so we always flush address 0.
*/
/*ARGSUSED*/
void
{
doflush(0);
}
/*
* Trapstat support for Niagara2 processor
* The Niagara2 provides HWTW support for TSB lookup and with HWTW
* enabled no TSB hit information will be available. Therefore setting
* the time spent in TLB miss handler for TSB hits to 0.
*/
int
{
int status = 0;
switch (cmd) {
case CPU_TSTATCONF_INIT:
case CPU_TSTATCONF_FINI:
case CPU_TSTATCONF_ENABLE:
case CPU_TSTATCONF_DISABLE:
break;
default:
break;
}
return (status);
}
void
{
int i;
for (i = 0; i < tstat_pgszs; i++, tstatp++) {
}
}
/*
* Page coloring support for hashed cache index mode
*/
/*
* Node id bits from machine description (MD). Node id distinguishes
* local versus remote memory. Because of MPO, page allocation does
* not cross node boundaries. Therefore, remove the node id bits from
* the color, since they are fixed. Either bit 30, or 31:30 in
* Victoria Falls processors.
* The number of node id bits is always 0 in Niagara2.
*/
typedef struct n2color {
} n2color_t;
/*
* Remove node id bits from color bits 32:28.
* This will reduce the number of colors.
* No change if number of node bits is zero.
*/
static inline uint_t
{
if (m.nnbits > 0) {
}
return (color);
}
/*
* Restore node id bits into page color.
* This will increase the number of colors to match N2.
* No change if number of node bits is zero.
*/
static inline uint_t
{
if (m.nnbits > 0) {
}
return (color);
}
/* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */
/*
* iterator NULL means pfn is VA, do not adjust ra_to_pa
* iterator (-1) means pfn is RA, need to convert to PA
* iterator non-null means pfn is RA, use ra_to_pa
*/
{
}
/* 19:18 */
}
}
static uint_t
{
/* 19:18 */
}
return (color);
}
#if TTE256M != 5
#endif
{
mask >>= 1;
}
{
color >>= 1;
}
{
uint_t s;
return (s);
}
{
return (color);
}
/*ARGSUSED*/
{
/* convert RA to PA for accurate color calculation */
/* first call after it, so cache these values */
it->mi_hash_color =
} else {
}
/* restart here when we switch memblocks */
/* we start from the page with correct color and mnode */
/* page color is PA[32:28] */
} else {
/* page color is PA[32:28].PA[19:19] */
}
/*
* Preserve mnode bits in case they are not part of the
* color mask (eg., 8GB interleave, mnode bits 34:33).
*/
goto done;
} else {
/*
* We deal 64K or 8K page. Check if we could the
* satisfy the request without changing PA[32:28]
*/
goto done;
/*
* for next pfn we have to change bits PA[32:28]
* set PA[63:28] and PA[19:18] of the next pfn
*/
/*
* set bits PA[17:13] to match the color
*/
goto done;
}
}
/*
* we start from the page with incorrect color - rare case
*/
/* page color is in bits PA[32:28] */
} else {
/* try get the right color by changing bit PA[19:19] */
goto done;
/* page color is PA[32:28].PA[19:19] */
}
/* Fix mnode if necessary */
/*
* Preserve mnode bits in case they are not part of the color
* mask eg 8GB interleave, mnode bits 34:33).
*/
}
goto done;
}
/*
* We deal 64K or 8K page of incorrect color.
* Try correcting color without changing PA[32:28]
*/
ceq_mask) == 0) {
/* the color is fixed - find the next page */
mask);
}
goto done;
}
}
/* to fix the color need to touch PA[32:28] */
/* fix mnode if input pfn is in the wrong mnode. */
}
}
/* set bits PA[19:13] to match the color */
done:
/* PA to RA */
/* check for possible memblock switch */
0);
return (pfn);
goto next_mem_block;
}
return (npfn);
}
/*
* init page coloring
* VF encodes node_id for an L-group in either bit 30 or 31:30,
* which effectively reduces the number of colors available per mnode.
*/
void
{
int i;
n2color_t m;
for (i = 0; i < max_mem_nodes; i++) {
break;
}
ASSERT(i < max_mem_nodes);
for (i = 0; i < mmu_page_sizes; i++) {
(void) memset(&m, 0, sizeof (m));
if (lo > 0) {
}
n2color[i] = m;
}
}
/*
* group colorequiv colors on N2 by low order bits of the color first
*/
void
{
if (colorequiv > 1) {
int i;
if (sv_a > 15)
sv_a = 15;
for (i = 0; i < MMU_PAGE_SIZES; i++) {
continue;
while ((colors >> a) == 0)
a--;
if (a > (colorequivszc[i] & 0xf) +
(colorequivszc[i] >> 4)) {
if (a <= nequiv_shades_log2[i]) {
colorequivszc[i] = (uchar_t)a;
} else {
colorequivszc[i] =
((a - nequiv_shades_log2[i]) << 4) |
}
}
}
}
}