niagara2.c revision 4496171313bed39e96f21bc2f9faf2868e267ae3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/archsystm.h>
#include <sys/machparam.h>
#include <sys/machsystm.h>
#include <sys/elf_SPARC.h>
#include <vm/hat_sfmmu.h>
#include <sys/dditypes.h>
#include <sys/cpu_module.h>
#include <sys/prom_debug.h>
#include <sys/prom_plat.h>
#include <sys/sysmacros.h>
#include <sys/machtrap.h>
#include <sys/simulate.h>
#include <sys/niagara2regs.h>
#include <sys/trapstat.h>
char cpu_module_name[] = "SUNW,UltraSPARC-T2";
/*
* Hypervisor services information for the NIAGARA2 CPU module
*/
static hsvc_info_t niagara2_hsvc = {
};
void
cpu_setup(void)
{
extern int mmu_exported_pagesize_mask;
extern int cpc_has_overflow_intr;
int status;
/*
* Negotiate the API version for Niagara2 specific hypervisor
* services.
*/
if (status != 0) {
"group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
}
/*
* The setup common to all CPU modules is done in cpu_setup_common
* routine.
*/
if ((mmu_exported_pagesize_mask &
" does not have required sun4v page sizes"
" 8K, 64K and 4M: MD mask is 0x%x",
/*
* Niagara2 supports a 48-bit subset of the full 64-bit virtual
* address space. Virtual addresses between 0x0000800000000000
* and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
* and must never be mapped. In addition, software must not use
* pages within 4GB of the VA hole as instruction pages to
* avoid problems with prefetching into the VA hole.
*/
/*
* Niagara2 has a performance counter overflow interrupt
*/
}
/*
* Set the magic constants of the implementation.
*/
void
{
/*
* The Cache node is optional in MD. Therefore in case "Cache"
* node does not exists in MD, set the default L2 cache associativity,
* size, linesize.
*/
if (cpunode->ecache_size == 0)
if (cpunode->ecache_linesize == 0)
if (cpunode->ecache_associativity == 0)
}
static int niagara2_cpucnt;
void
{
extern int niagara_kstat_init(void);
/*
* The cpu_ipipe field is initialized based on the execution
* unit sharing information from the MD. It defaults to the
* virtual CPU id in the absence of such information.
*/
(void) niagara_kstat_init();
}
/*ARGSUSED*/
void
{
extern int niagara_kstat_fini(void);
(void) niagara_kstat_fini();
}
/*
* On Niagara2, any flush will cause all preceding stores to be
* synchronized wrt the i$, regardless of address or ASI. In fact,
* the address is ignored, so we always flush address 0.
*/
/*ARGSUSED*/
void
{
doflush(0);
}
/*
* Trapstat support for Niagara2 processor
* The Niagara2 provides HWTW support for TSB lookup and with HWTW
* enabled no TSB hit information will be available. Therefore setting
* the time spent in TLB miss handler for TSB hits to 0.
*/
int
cpu_trapstat_conf(int cmd)
{
int status = 0;
switch (cmd) {
case CPU_TSTATCONF_INIT:
case CPU_TSTATCONF_FINI:
case CPU_TSTATCONF_ENABLE:
case CPU_TSTATCONF_DISABLE:
break;
default:
break;
}
return (status);
}
void
{
int i;
for (i = 0; i < tstat_pgszs; i++, tstatp++) {
}
}