niagara2.c revision 59ac0c1669407488b67ae9e273667a340dccc611
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER START
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The contents of this file are subject to the terms of the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Common Development and Distribution License (the "License").
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You may not use this file except in compliance with the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4496171313bed39e96f21bc2f9faf2868e267ae3girish * or http://www.opensolaris.org/os/licensing.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * See the License for the specific language governing permissions
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and limitations under the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * When distributing Covered Code, include this CDDL HEADER in each
4496171313bed39e96f21bc2f9faf2868e267ae3girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * If applicable, add the following below this CDDL HEADER, with the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * fields enclosed by brackets "[]" replaced with your own identifying
4496171313bed39e96f21bc2f9faf2868e267ae3girish * information: Portions Copyright [yyyy] [name of copyright owner]
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER END
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Use is subject to license terms.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#pragma ident "%Z%%M% %I% %E% SMI"
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/types.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/systm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/archsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machparam.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpu.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/elf_SPARC.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <vm/hat_sfmmu.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <vm/page.h>
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp#include <vm/vm_dep.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpuvar.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/async.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cmn_err.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/debug.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/dditypes.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/sunddi.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpu_module.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/prom_debug.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/vmsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/prom_plat.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/sysmacros.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/intreg.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machtrap.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/ontrap.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/ivintr.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/atomic.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/panic.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/dtrace.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/simulate.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/fault.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/niagara2regs.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/hsvc.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/trapstat.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishuint_t root_phys_addr_lo_mask = 0xffffffffU;
59ac0c1669407488b67ae9e273667a340dccc611davemq#if defined(NIAGARA2_IMPL)
4496171313bed39e96f21bc2f9faf2868e267ae3girishchar cpu_module_name[] = "SUNW,UltraSPARC-T2";
59ac0c1669407488b67ae9e273667a340dccc611davemq#elif defined(VFALLS_IMPL)
59ac0c1669407488b67ae9e273667a340dccc611davemqchar cpu_module_name[] = "SUNW,UltraSPARC-T2+";
59ac0c1669407488b67ae9e273667a340dccc611davemq#endif
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
59ac0c1669407488b67ae9e273667a340dccc611davemq * Hypervisor services information for the NIAGARA2 and Victoria Falls
59ac0c1669407488b67ae9e273667a340dccc611davemq * CPU module
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
59ac0c1669407488b67ae9e273667a340dccc611davemqstatic boolean_t cpu_hsvc_available = B_TRUE;
59ac0c1669407488b67ae9e273667a340dccc611davemqstatic uint64_t cpu_sup_minor; /* Supported minor number */
59ac0c1669407488b67ae9e273667a340dccc611davemq#if defined(NIAGARA2_IMPL)
59ac0c1669407488b67ae9e273667a340dccc611davemqstatic hsvc_info_t cpu_hsvc = {
4496171313bed39e96f21bc2f9faf2868e267ae3girish HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR,
4496171313bed39e96f21bc2f9faf2868e267ae3girish NIAGARA2_HSVC_MINOR, cpu_module_name
4496171313bed39e96f21bc2f9faf2868e267ae3girish};
59ac0c1669407488b67ae9e273667a340dccc611davemq#elif defined(VFALLS_IMPL)
59ac0c1669407488b67ae9e273667a340dccc611davemqstatic hsvc_info_t cpu_hsvc = {
59ac0c1669407488b67ae9e273667a340dccc611davemq HSVC_REV_1, NULL, HSVC_GROUP_VFALLS_CPU, VFALLS_HSVC_MAJOR,
59ac0c1669407488b67ae9e273667a340dccc611davemq VFALLS_HSVC_MINOR, cpu_module_name
59ac0c1669407488b67ae9e273667a340dccc611davemq};
59ac0c1669407488b67ae9e273667a340dccc611davemq#endif
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_setup(void)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int mmu_exported_pagesize_mask;
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int cpc_has_overflow_intr;
aaa10e6791d1614700651df2821f84d490c094bfha extern size_t contig_mem_prealloc_base;
4496171313bed39e96f21bc2f9faf2868e267ae3girish int status;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Negotiate the API version for Niagara2 specific hypervisor
4496171313bed39e96f21bc2f9faf2868e267ae3girish * services.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
59ac0c1669407488b67ae9e273667a340dccc611davemq status = hsvc_register(&cpu_hsvc, &cpu_sup_minor);
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (status != 0) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services "
4496171313bed39e96f21bc2f9faf2868e267ae3girish "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
59ac0c1669407488b67ae9e273667a340dccc611davemq cpu_hsvc.hsvc_modname, cpu_hsvc.hsvc_group,
59ac0c1669407488b67ae9e273667a340dccc611davemq cpu_hsvc.hsvc_major, cpu_hsvc.hsvc_minor, status);
59ac0c1669407488b67ae9e273667a340dccc611davemq cpu_hsvc_available = B_FALSE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The setup common to all CPU modules is done in cpu_setup_common
4496171313bed39e96f21bc2f9faf2868e267ae3girish * routine.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpu_setup_common(NULL);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish cache |= (CACHE_PTAG | CACHE_IOCOHERENT);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish if ((mmu_exported_pagesize_mask &
4496171313bed39e96f21bc2f9faf2868e267ae3girish DEFAULT_SUN4V_MMU_PAGESIZE_MASK) !=
4496171313bed39e96f21bc2f9faf2868e267ae3girish DEFAULT_SUN4V_MMU_PAGESIZE_MASK)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cmn_err(CE_PANIC, "machine description"
4496171313bed39e96f21bc2f9faf2868e267ae3girish " does not have required sun4v page sizes"
4496171313bed39e96f21bc2f9faf2868e267ae3girish " 8K, 64K and 4M: MD mask is 0x%x",
4496171313bed39e96f21bc2f9faf2868e267ae3girish mmu_exported_pagesize_mask);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Niagara2 supports a 48-bit subset of the full 64-bit virtual
4496171313bed39e96f21bc2f9faf2868e267ae3girish * address space. Virtual addresses between 0x0000800000000000
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and must never be mapped. In addition, software must not use
4496171313bed39e96f21bc2f9faf2868e267ae3girish * pages within 4GB of the VA hole as instruction pages to
4496171313bed39e96f21bc2f9faf2868e267ae3girish * avoid problems with prefetching into the VA hole.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32));
4496171313bed39e96f21bc2f9faf2868e267ae3girish hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32));
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Niagara2 has a performance counter overflow interrupt
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpc_has_overflow_intr = 1;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * Enable 4M pages for OOB.
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp max_uheap_lpsize = MMU_PAGESIZE4M;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp max_ustack_lpsize = MMU_PAGESIZE4M;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp max_privmap_lpsize = MMU_PAGESIZE4M;
aaa10e6791d1614700651df2821f84d490c094bfha
aaa10e6791d1614700651df2821f84d490c094bfha contig_mem_prealloc_base = NIAGARA2_PREALLOC_BASE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Set the magic constants of the implementation.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_fiximp(struct cpu_node *cpunode)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The Cache node is optional in MD. Therefore in case "Cache"
4496171313bed39e96f21bc2f9faf2868e267ae3girish * node does not exists in MD, set the default L2 cache associativity,
4496171313bed39e96f21bc2f9faf2868e267ae3girish * size, linesize.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_size == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_size = L2CACHE_SIZE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_linesize == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_linesize = L2CACHE_LINESIZE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_associativity == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY;
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
459190a5c46206e7885f6a649a055ceb46be49a7rsmaedacpu_map_exec_units(struct cpu *cp)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda ASSERT(MUTEX_HELD(&cpu_lock));
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe * The cpu_ipipe and cpu_fpu fields are initialized based on
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda * the execution unit sharing information from the MD. They
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda * default to the CPU id in the absence of such information.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping;
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND)
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id);
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe /*
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe * Niagara 2 defines the core to be at the FPU level
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe */
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu;
59ac0c1669407488b67ae9e273667a340dccc611davemq
59ac0c1669407488b67ae9e273667a340dccc611davemq /*
59ac0c1669407488b67ae9e273667a340dccc611davemq * The cpu_chip field is initialized based on the information
59ac0c1669407488b67ae9e273667a340dccc611davemq * in the MD and assume that all cpus within a chip
59ac0c1669407488b67ae9e273667a340dccc611davemq * share the same L2 cache. If no such info is available, we
59ac0c1669407488b67ae9e273667a340dccc611davemq * set the cpu to belong to the defacto chip 0.
59ac0c1669407488b67ae9e273667a340dccc611davemq */
59ac0c1669407488b67ae9e273667a340dccc611davemq cp->cpu_m.cpu_chip = cpunodes[cp->cpu_id].l2_cache_mapping;
59ac0c1669407488b67ae9e273667a340dccc611davemq if (cp->cpu_m.cpu_chip == NO_CHIP_MAPPING_FOUND)
59ac0c1669407488b67ae9e273667a340dccc611davemq cp->cpu_m.cpu_chip = 0;
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda}
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda
59ac0c1669407488b67ae9e273667a340dccc611davemqstatic int cpucnt;
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda
459190a5c46206e7885f6a649a055ceb46be49a7rsmaedavoid
459190a5c46206e7885f6a649a055ceb46be49a7rsmaedacpu_init_private(struct cpu *cp)
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda{
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda extern void niagara_kstat_init(void);
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe
4496171313bed39e96f21bc2f9faf2868e267ae3girish ASSERT(MUTEX_HELD(&cpu_lock));
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda cpu_map_exec_units(cp);
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda
59ac0c1669407488b67ae9e273667a340dccc611davemq if ((cpucnt++ == 0) && (cpu_hsvc_available == B_TRUE))
59ac0c1669407488b67ae9e273667a340dccc611davemq (void) niagara_kstat_init();
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_uninit_private(struct cpu *cp)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
459190a5c46206e7885f6a649a055ceb46be49a7rsmaeda extern void niagara_kstat_fini(void);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish ASSERT(MUTEX_HELD(&cpu_lock));
59ac0c1669407488b67ae9e273667a340dccc611davemq if ((--cpucnt == 0) && (cpu_hsvc_available == B_TRUE))
59ac0c1669407488b67ae9e273667a340dccc611davemq (void) niagara_kstat_fini();
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * On Niagara2, any flush will cause all preceding stores to be
4496171313bed39e96f21bc2f9faf2868e267ae3girish * synchronized wrt the i$, regardless of address or ASI. In fact,
4496171313bed39e96f21bc2f9faf2868e267ae3girish * the address is ignored, so we always flush address 0.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishdtrace_flush_sec(uintptr_t addr)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish doflush(0);
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Trapstat support for Niagara2 processor
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The Niagara2 provides HWTW support for TSB lookup and with HWTW
4496171313bed39e96f21bc2f9faf2868e267ae3girish * enabled no TSB hit information will be available. Therefore setting
4496171313bed39e96f21bc2f9faf2868e267ae3girish * the time spent in TLB miss handler for TSB hits to 0.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girishint
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_trapstat_conf(int cmd)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish int status = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish switch (cmd) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_INIT:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_FINI:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_ENABLE:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_DISABLE:
4496171313bed39e96f21bc2f9faf2868e267ae3girish break;
4496171313bed39e96f21bc2f9faf2868e267ae3girish default:
4496171313bed39e96f21bc2f9faf2868e267ae3girish status = EINVAL;
4496171313bed39e96f21bc2f9faf2868e267ae3girish break;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish return (status);
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_trapstat_data(void *buf, uint_t tstat_pgszs)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf;
4496171313bed39e96f21bc2f9faf2868e267ae3girish int i;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish for (i = 0; i < tstat_pgszs; i++, tstatp++) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp/* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dpuint_t
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_pfn_2_color_cpu(pfn_t pfn, uchar_t szc)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp uint_t color;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT(szc <= TTE256M);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn = PFN_BASE(pfn, szc);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp color = ((pfn >> 15) ^ pfn) & 0x1f;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc >= TTE4M)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (color);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp color = (color << 2) | ((pfn >> 5) & 0x3);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (szc <= TTE64K ? color : (color >> 1));
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp#if TTE256M != 5
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp#error TTE256M is not 5
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp#endif
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dpuint_t
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f};
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT(szc < TTE256M);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp mask &= ni2_color_masks[szc];
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return ((szc == TTE64K || szc == TTE512K) ? (mask >> 1) : mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dpuint_t
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_get_nsz_color_cpu(uchar_t szc, uint_t color)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT(szc < TTE256M);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return ((szc == TTE64K || szc == TTE512K) ? (color >> 1) : color);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dpuint_t
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_get_color_shift_cpu(uchar_t szc, uchar_t nszc)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
ef29e9078142ba78702f73f4854d952174aca80bsusans ASSERT(nszc >= szc);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT(nszc <= TTE256M);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
ef29e9078142ba78702f73f4854d952174aca80bsusans if (szc == nszc)
ef29e9078142ba78702f73f4854d952174aca80bsusans return (0);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc <= TTE64K)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return ((nszc >= TTE4M) ? 2 : ((nszc >= TTE512K) ? 1 : 0));
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc == TTE512K)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (1);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (0);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp/*ARGSUSED*/
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppfn_t
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color,
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp uint_t ceq_mask, uint_t color_mask)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_t pstep = PNUM_SIZE(szc);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_t npfn, pfn_ceq_mask, pfn_color;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_t tmpmask, mask = (pfn_t)-1;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT((color & ~ceq_mask) == 0);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (((page_pfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* we start from the page with correct color */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc >= TTE512K) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc >= TTE4M) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* page color is PA[32:28] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = ceq_mask << 15;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp } else {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* page color is PA[32:28].PA[19:19] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = ((ceq_mask & 1) << 6) |
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ((ceq_mask >> 1) << 15);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (pfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp } else {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * We deal 64K or 8K page. Check if we could the
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * satisfy the request without changing PA[32:28]
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if ((((npfn ^ pfn) >> 15) & 0x1f) == 0)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * for next pfn we have to change bits PA[32:28]
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * set PA[63:28] and PA[19:18] of the next pfn
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = (pfn >> 15) << 15;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn |= (ceq_mask & color & 3) << 5;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = (szc == TTE8K) ? 0 :
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp (ceq_mask & 0x1c) << 13;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * set bits PA[17:13] to match the color
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ceq_mask >>= 2;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp color = (color >> 2) & ceq_mask;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn |= ((npfn >> 15) ^ color) & ceq_mask;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * we start from the page with incorrect color - rare case
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc >= TTE512K) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (szc >= TTE4M) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* page color is in bits PA[32:28] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ((pfn >> 20) << 20) | (color << 15);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = (ceq_mask << 15) | 0x7fff;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp } else {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* try get the right color by changing bit PA[19:19] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = pfn + pstep;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (((page_pfn_2_color_cpu(npfn, szc) ^ color) &
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ceq_mask) == 0)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* page color is PA[32:28].PA[19:19] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = ((ceq_mask & 1) << 6) |
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ((ceq_mask >> 1) << 15) | (0xff << 7);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_color = ((color & 1) << 6) | ((color >> 1) << 15);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ((pfn >> 20) << 20) | pfn_color;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp while (npfn <= pfn) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * We deal 64K or 8K page of incorrect color.
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * Try correcting color without changing PA[32:28]
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp pfn_color = ((color & 3) << 5) | (color >> 2);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = (pfn & ~(pfn_t)0x7f);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* the color is fixed - find the next page */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp while (npfn <= pfn) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp if ((((npfn ^ pfn) >> 15) & 0x1f) == 0)
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* to fix the color need to touch PA[32:28] */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) :
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp (((pfn >> 18) << 18) | ((color & 0x1c) << 13));
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp while (npfn <= pfn) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp /* set bits PA[19:13] to match the color */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp ASSERT(((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp return (npfn);
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp/*
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp * init page coloring
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp */
102033aa92edf302ad31b3bdd7c6fcd2d6910903dpvoid
102033aa92edf302ad31b3bdd7c6fcd2d6910903dppage_coloring_init_cpu()
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp{
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp int i;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp hw_page_array[0].hp_colors = 1 << 7;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp hw_page_array[1].hp_colors = 1 << 7;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp hw_page_array[2].hp_colors = 1 << 6;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp for (i = 3; i < mmu_page_sizes; i++) {
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp hw_page_array[i].hp_colors = 1 << 5;
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp }
102033aa92edf302ad31b3bdd7c6fcd2d6910903dp}
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp/*
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp * group colorequiv colors on N2 by low order bits of the color first
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp */
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdpvoid
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdppage_set_colorequiv_arr_cpu(void)
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp{
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0};
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp if (colorequiv > 1) {
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp int i;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp uint_t sv_a = lowbit(colorequiv) - 1;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp if (sv_a > 15)
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp sv_a = 15;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp for (i = 0; i < MMU_PAGE_SIZES; i++) {
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp uint_t colors;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp uint_t a = sv_a;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp if ((colors = hw_page_array[i].hp_colors) <= 1)
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp continue;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp while ((colors >> a) == 0)
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp a--;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp if (a > (colorequivszc[i] & 0xf) +
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp (colorequivszc[i] >> 4)) {
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp if (a <= nequiv_shades_log2[i]) {
59ac0c1669407488b67ae9e273667a340dccc611davemq colorequivszc[i] = (uchar_t)a;
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp } else {
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp colorequivszc[i] =
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp ((a - nequiv_shades_log2[i]) << 4) |
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp nequiv_shades_log2[i];
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp }
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp }
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp }
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp }
fe70c9cf90dfc23d18485fb7b4b20a1175d53a8bdp}