niagara2.c revision 4496171313bed39e96f21bc2f9faf2868e267ae3
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER START
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The contents of this file are subject to the terms of the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Common Development and Distribution License (the "License").
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You may not use this file except in compliance with the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4496171313bed39e96f21bc2f9faf2868e267ae3girish * or http://www.opensolaris.org/os/licensing.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * See the License for the specific language governing permissions
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and limitations under the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * When distributing Covered Code, include this CDDL HEADER in each
4496171313bed39e96f21bc2f9faf2868e267ae3girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * If applicable, add the following below this CDDL HEADER, with the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * fields enclosed by brackets "[]" replaced with your own identifying
4496171313bed39e96f21bc2f9faf2868e267ae3girish * information: Portions Copyright [yyyy] [name of copyright owner]
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER END
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Use is subject to license terms.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#pragma ident "%Z%%M% %I% %E% SMI"
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/types.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/systm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/archsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machparam.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpu.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/elf_SPARC.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <vm/hat_sfmmu.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <vm/page.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpuvar.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/async.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cmn_err.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/debug.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/dditypes.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/sunddi.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/cpu_module.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/prom_debug.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/vmsystm.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/prom_plat.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/sysmacros.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/intreg.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machtrap.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/ontrap.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/ivintr.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/atomic.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/panic.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/dtrace.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/simulate.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/fault.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/niagara2regs.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/hsvc.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/trapstat.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishuint_t root_phys_addr_lo_mask = 0xffffffffU;
4496171313bed39e96f21bc2f9faf2868e267ae3girishchar cpu_module_name[] = "SUNW,UltraSPARC-T2";
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Hypervisor services information for the NIAGARA2 CPU module
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girishstatic boolean_t niagara2_hsvc_available = B_TRUE;
4496171313bed39e96f21bc2f9faf2868e267ae3girishstatic uint64_t niagara2_sup_minor; /* Supported minor number */
4496171313bed39e96f21bc2f9faf2868e267ae3girishstatic hsvc_info_t niagara2_hsvc = {
4496171313bed39e96f21bc2f9faf2868e267ae3girish HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR,
4496171313bed39e96f21bc2f9faf2868e267ae3girish NIAGARA2_HSVC_MINOR, cpu_module_name
4496171313bed39e96f21bc2f9faf2868e267ae3girish};
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_setup(void)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int mmu_exported_pagesize_mask;
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int cpc_has_overflow_intr;
4496171313bed39e96f21bc2f9faf2868e267ae3girish int status;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Negotiate the API version for Niagara2 specific hypervisor
4496171313bed39e96f21bc2f9faf2868e267ae3girish * services.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor);
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (status != 0) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services "
4496171313bed39e96f21bc2f9faf2868e267ae3girish "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
4496171313bed39e96f21bc2f9faf2868e267ae3girish niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group,
4496171313bed39e96f21bc2f9faf2868e267ae3girish niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status);
4496171313bed39e96f21bc2f9faf2868e267ae3girish niagara2_hsvc_available = B_FALSE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The setup common to all CPU modules is done in cpu_setup_common
4496171313bed39e96f21bc2f9faf2868e267ae3girish * routine.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpu_setup_common(NULL);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish cache |= (CACHE_PTAG | CACHE_IOCOHERENT);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish if ((mmu_exported_pagesize_mask &
4496171313bed39e96f21bc2f9faf2868e267ae3girish DEFAULT_SUN4V_MMU_PAGESIZE_MASK) !=
4496171313bed39e96f21bc2f9faf2868e267ae3girish DEFAULT_SUN4V_MMU_PAGESIZE_MASK)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cmn_err(CE_PANIC, "machine description"
4496171313bed39e96f21bc2f9faf2868e267ae3girish " does not have required sun4v page sizes"
4496171313bed39e96f21bc2f9faf2868e267ae3girish " 8K, 64K and 4M: MD mask is 0x%x",
4496171313bed39e96f21bc2f9faf2868e267ae3girish mmu_exported_pagesize_mask);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Niagara2 supports a 48-bit subset of the full 64-bit virtual
4496171313bed39e96f21bc2f9faf2868e267ae3girish * address space. Virtual addresses between 0x0000800000000000
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and must never be mapped. In addition, software must not use
4496171313bed39e96f21bc2f9faf2868e267ae3girish * pages within 4GB of the VA hole as instruction pages to
4496171313bed39e96f21bc2f9faf2868e267ae3girish * avoid problems with prefetching into the VA hole.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32));
4496171313bed39e96f21bc2f9faf2868e267ae3girish hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32));
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Niagara2 has a performance counter overflow interrupt
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpc_has_overflow_intr = 1;
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Set the magic constants of the implementation.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_fiximp(struct cpu_node *cpunode)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The Cache node is optional in MD. Therefore in case "Cache"
4496171313bed39e96f21bc2f9faf2868e267ae3girish * node does not exists in MD, set the default L2 cache associativity,
4496171313bed39e96f21bc2f9faf2868e267ae3girish * size, linesize.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_size == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_size = L2CACHE_SIZE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_linesize == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_linesize = L2CACHE_LINESIZE;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cpunode->ecache_associativity == 0)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY;
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishstatic int niagara2_cpucnt;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_init_private(struct cpu *cp)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int niagara_kstat_init(void);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The cpu_ipipe field is initialized based on the execution
4496171313bed39e96f21bc2f9faf2868e267ae3girish * unit sharing information from the MD. It defaults to the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * virtual CPU id in the absence of such information.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
4496171313bed39e96f21bc2f9faf2868e267ae3girish if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
4496171313bed39e96f21bc2f9faf2868e267ae3girish cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish ASSERT(MUTEX_HELD(&cpu_lock));
4496171313bed39e96f21bc2f9faf2868e267ae3girish if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE))
4496171313bed39e96f21bc2f9faf2868e267ae3girish (void) niagara_kstat_init();
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_uninit_private(struct cpu *cp)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish extern int niagara_kstat_fini(void);
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish ASSERT(MUTEX_HELD(&cpu_lock));
4496171313bed39e96f21bc2f9faf2868e267ae3girish if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE))
4496171313bed39e96f21bc2f9faf2868e267ae3girish (void) niagara_kstat_fini();
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * On Niagara2, any flush will cause all preceding stores to be
4496171313bed39e96f21bc2f9faf2868e267ae3girish * synchronized wrt the i$, regardless of address or ASI. In fact,
4496171313bed39e96f21bc2f9faf2868e267ae3girish * the address is ignored, so we always flush address 0.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishdtrace_flush_sec(uintptr_t addr)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish doflush(0);
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Trapstat support for Niagara2 processor
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The Niagara2 provides HWTW support for TSB lookup and with HWTW
4496171313bed39e96f21bc2f9faf2868e267ae3girish * enabled no TSB hit information will be available. Therefore setting
4496171313bed39e96f21bc2f9faf2868e267ae3girish * the time spent in TLB miss handler for TSB hits to 0.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girishint
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_trapstat_conf(int cmd)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish int status = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish switch (cmd) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_INIT:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_FINI:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_ENABLE:
4496171313bed39e96f21bc2f9faf2868e267ae3girish case CPU_TSTATCONF_DISABLE:
4496171313bed39e96f21bc2f9faf2868e267ae3girish break;
4496171313bed39e96f21bc2f9faf2868e267ae3girish default:
4496171313bed39e96f21bc2f9faf2868e267ae3girish status = EINVAL;
4496171313bed39e96f21bc2f9faf2868e267ae3girish break;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish return (status);
4496171313bed39e96f21bc2f9faf2868e267ae3girish}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_trapstat_data(void *buf, uint_t tstat_pgszs)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf;
4496171313bed39e96f21bc2f9faf2868e267ae3girish int i;
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish for (i = 0; i < tstat_pgszs; i++, tstatp++) {
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
4496171313bed39e96f21bc2f9faf2868e267ae3girish }
4496171313bed39e96f21bc2f9faf2868e267ae3girish}