/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <vm/hat_sfmmu.h>
#include <sys/sysmacros.h>
#include <sys/machparam.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/vm_machparam.h>
#include <sys/prom_isa.h>
#include <sys/prom_plat.h>
#include <sys/prom_debug.h>
#include <sys/privregs.h>
#include <sys/bootconf.h>
#include <sys/memlist_plat.h>
#include <sys/cpu_module.h>
/*
* External routines and data structures
*/
extern void sfmmu_cache_flushcolor(int, pfn_t);
/*
* Static routines
*/
static void sfmmu_set_tlb(void);
/*
* Global Data:
*/
int bigktsb_nttes = 0;
/*
* Controls the logic which enables the use of the
* QUAD_LDD_PHYS ASI for TSB accesses.
*/
int ktsb_phys = 0;
/*
* This routine remaps the kernel using large ttes
* All entries except locked ones will be removed from the tlb.
* It assumes that both the text and data segments reside in a separate
* 4mb virtual and physical contigous memory chunk. This routine
* is only executed by the first cpu. The remaining cpus execute
* sfmmu_mp_startup() instead.
* XXX It assumes that the start of the text segment is KERNELBASE. It should
* actually be based on start.
*/
void
sfmmu_remap_kernel(void)
{
int flags;
extern char end[];
if (pfn == PFN_INVALID)
prom_panic("can't find kernel text pfn");
/*
* We set the lock bit in the tte to lock the translation in
* the tlb. Note we cannot lock Panther 32M/256M pages into the tlb.
* This note is here to make sure that no one tries to remap the
* kernel using 32M or 256M tte's on Panther cpus.
*/
if (pfn == PFN_INVALID)
prom_panic("can't find kernel data pfn");
/*
* We set the lock bit in the tte to lock the translation in
* the tlb. We also set the mod bit to avoid taking dirty bit
* traps on kernel data.
*/
/*
* create bigktsb ttes if necessary.
*/
if (enable_bigktsb) {
int i = 0;
while (tsbsz != 0) {
ASSERT(i < MAX_BIGKTSB_TTES);
/*
* No need to lock if we use physical addresses.
* Since we invalidate the kernel TSB using virtual
* addresses, it's an optimization to load them now
* so that we won't have to load them later.
*/
if (!ktsb_phys) {
}
bigktsb_ttes[i] = tte;
va += MMU_PAGESIZE4M;
tsbsz -= MMU_PAGESIZE4M;
i++;
}
bigktsb_nttes = i;
}
}
#ifndef UTSB_PHYS
/*
* Unmap all references to user TSBs from the TLB of the current processor.
*/
static void
{
/* Demap all pages in the VA range for the first user TSB */
va = utsb_vabase;
va += MMU_PAGESIZE;
}
/* Demap all pages in the VA range for the second user TSB */
va = utsb4m_vabase;
va += MMU_PAGESIZE;
}
}
#endif /* UTSB_PHYS */
/*
* Setup the kernel's locked tte's
*/
void
sfmmu_set_tlb(void)
{
/*
* NOTE: the prom will do an explicit unmap of the VAs from the TLBs
* in the following functions before loading the new value into the
* TLB. Thus if there was an entry already in the TLB at a different
* location, it will get unmapped before we load the entry at the
* specified location.
*/
index -= 3;
#ifndef UTSB_PHYS
utsb_dtlb_ttenum = index--;
utsb4m_dtlb_ttenum = index--;
#endif /* UTSB_PHYS */
if (!ktsb_phys && enable_bigktsb) {
int i;
for (i = 0; i < bigktsb_nttes; i++) {
va += MMU_PAGESIZE4M;
index--;
}
}
}
/*
* This routine is executed by all other cpus except the first one
* at initialization time. It is responsible for taking over the
* mmu from the prom. We follow these steps.
* Lock the kernel's ttes in the TLB
* Initialize the tsb hardware registers
* Take over the trap table
* Flush the prom's locked entries from the TLB
*/
void
sfmmu_mp_startup(void)
{
}
void
{
if (do_dtlb)
}
/*ARGSUSED*/
void
{
}
/* clear user TSB information (applicable to hardware TSB walkers) */
void
{
}
/*ARGSUSED*/
void
{
}
/*
* Invalidate a TSB. If floating point is enabled we use
* a fast block-store routine, otherwise we use the old method
* of walking the TSB setting each tag to TSBTAG_INVALID.
*/
void
{
/* CONSTCOND */
if (fpu_exists) {
return;
}
tsbaddr++) {
}
}
/*
* Completely flush the D-cache on all cpus.
*/
void
{
int i;
for (i = 0; i < CACHE_NUM_COLOR; i++)
sfmmu_cache_flushcolor(i, 0);
}