/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_SPITREGS_H
#define _SYS_SPITREGS_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is cpu dependent.
*/
#ifdef _STARFIRE
/*
* Starfire's cpu upaids are not the same
* as cpuids.
* XXX - our obp took the liberty of
* converting cpu upaids into cpuids when
* presenting it as upa-portid property.
*/
(upaid &0x3))
#else
/*
* The mid is the same as the cpu id.
* We might want to change this later
*/
#endif /* _STARFIRE */
/*
* LSU Control Register
*
* +------+----+----+----+----+----+----+-----+------+----+----+----+---+
* | Resv | PM | VM | PR | PW | VR | VW | Rsv | FM | DM | IM | DC | IC|
* +------+----+----+----+----+----+----+-----+------+----+----+----+---+
* 63 41 33 25 24 23 22 21 20 19 4 3 2 1 0
*
*/
/*
* Defines for the different types of dcache_flush
* it is stored in dflush_type
*/
/* each line for a match */
/* each line for a match */
/*
* D-Cache Tag Data Register
*
* +----------+--------+----------+
* | Reserved | DC_Tag | DC_Valid |
* +----------+--------+----------+
* 63 30 29 2 1 0
*
*/
/*
* Definitions of sun4u cpu implementations as specified in version register
*/
/*
* Bits of Spitfire Asynchronous Fault Status Register
*/
/*
* All error types
*/
/*
* Shifts for Spitfire Asynchronous Fault Status Register
*/
/*
* AFSR error bits for AFT Level 1 messages (uncorrected + parity + BERR + TO)
*/
/*
* Bits of Spitfire Asynchronous Fault Status Register
*/
/*
* Bits of Spitfire Asynchronous Fault Address Register
* The Sabre AFAR includes more bits since it only has a UDBH, no UDBL
*/
/*
* Bits of Spitfire/Sabre/Hummingbird Error Enable Registers
*/
/*
* Bits and vaddrs of Spitfire Datapath Error Registers
*/
/*
* Bits of Spitfire Datapath Control Register
*/
/*
* Bits and shifts for the Spitfire (S), Sabre (SB) and Hummingbird (HB)
* Ecache tag data
*/
/*
* Constants representing the complete Spitfire (S), Sabre (SB) and Hummingbird
* (HB) tag state:
*/
/*
* Constants representing the individual Spitfire (S), Sabre (SB) and
* Hummingbird (HB) state bits:
*/
/*
* Constants representing the individual Spitfire (S), Sabre (SB) and
* Hummingbird (HB) state parity and address parity bits:
*/
#ifdef HUMMINGBIRD
/* refresh interval */
/* works for all DIMM */
/* same value as OBP */
/*
* UPA Configuration Register
*
* +--------------+----+------+------+----------+------+-------------+
* | Resv | RR | DM | ELIM | PCON | MID | PCAP |
* +--------------+----+------+------+----------+------+-------------+
* 63 39 38 37..36 35..33 32......22 21..17 16..........0
*
*/
#endif /* HUMMINGBIRD */
/*
* The minimum size needed to ensure consistency on a virtually address
* cache. Computed by taking the largest virtually indexed cache and dividing
* by its associativity.
*/
#ifdef _KERNEL
#ifndef _ASM
/*
* The scrub_misc structure contains miscellaneous bookeepping items for
* scrubbing the E$.
*
* Counter of outstanding E$ scrub requests. The counter for a given CPU id
* is atomically incremented and decremented _only_ on that CPU,
* to avoid cacheline ownership bouncing.
*/
typedef struct spitfire_scrub_misc {
/*
* Spitfire module private data structure. One of these is allocated for each
* valid cpu at setup time and is pointed to by the machcpu "cpu_private"
* pointer.
*/
typedef struct spitfire_private {
#endif /* !_ASM */
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_SPITREGS_H */