/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCISCH_H
#define _SYS_PCISCH_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Performance counters information.
*/
/*
* Schizo-specific register offsets & bit field positions.
*/
/*
* [msb] [lsb]
* 0x00 <chip_type> <version#> <module-revision#>
*/
/*
* Offsets of Control Block registers ("reg" property 2nd entry)
*/
/*
* Tomatillo only bits in IOMMU control registers.
*/
/*
* Offsets of performance monitoring registers.
*/
/*
* Offsets of registers in the PBM block:
*/
/*
* Offsets of IO Cache Registers:
*/
/*
* Offsets of registers in the iommu block:
*/
/*
* Offsets of registers in the streaming cache block:
*/
/*
* MAX_PRF when enabled will always prefetch the max of 8
* prefetches if possible.
*/
/*
* Offsets of registers in the PCI Idle Check Diagnostics Register.
*/
/*
* Offsets of registers in the interrupt block:
*/
/*
* Address space offsets and sizes:
*/
/*
* Schizo-specific fields of interrupt mapping register:
*/
/*
* schizo ECC UE AFSR bit definitions:
*/
#define SCHIZO_ECC_UE_AFSR_SYND_SHIFT 0
/*
* schizo ECC CE AFSR bit definitions:
*/
#define SCHIZO_ECC_CE_AFSR_SYND_SHIFT 0
/*
*/
/*
* schizo pci control register bits:
*/
/*
* schizo PCI asynchronous fault status register bit definitions:
*/
/* Used for the tomatillo micro tlb bug. errata #82 */
/* Tomatillo control block JBUS error log bits */
#define XMITS_PCIX_MSG_MASK \
((afsr & SCHIZO_PCI_AFSR_DWORDMASK) >> \
/*
* XMITS Upper Retry Counter Register (bits 15:0)
*/
/*
* XMITS PCI-X Diagnostic Register bit definitions
*/
#define XMITS_PCI_X_DIAG_SRCQ_FLUSH_SHIFT 0
/*
* XMITS PCI-X Error Status Register bit definitions
*/
/*
* As a workaround for an XMITS ASIC bug, the following PCI-X errors are
* assigned new bit positions within the PCI-X Error Status Register to
* match what is actually implemented in the XMITS ASIC:
*
* Spec New
* Error Bit Position Bit Position
* -------------------- ------------ ------------
* XMITS_PCIX_STAT_SMMU 0x8ull 0x4ull
* XMITS_PCIX_STAT_SDSTAT 0x4ull 0x8ull
* XMITS_PCIX_STAT_CMMU 0x2ull 0x1ull
* XMITS_PCIX_STAT_CDSTAT 0x1ull 0x2ull
*
*/
/*
* PCI-X Message Classes and Indexes
*/
#define PCIX_SINGLE_ERR 0
/*
* Nested message structure to allow for storing all the PCI-X
* split completion messages in tabular form.
*/
typedef struct pcix_err_msg_rec {
char *msg_class;
char *msg_str;
typedef struct pcix_err_tbl {
/*
* Tomatillo IO Cache CSR bit definitions:
*/
/*
* schizo PCI diagnostic register bit definitions:
*/
/*
* schizo IOMMU TLB TAG diagnostic register bits
*/
#define TLBTAG_ERRSTAT_PROT 0
/*
* schizo IOMMU TLB Data RAM diagnostic register bits
*/
/*
* pbm_cdma_flag(schizo only): consistent dma sync handshake
*/
/*
* Estar control bit for schizo estar reg
*/
/*
* Tomatillo only
*/
/*
* Mask to tell which PCI Side we are on
*/
/*
* Offset from Schizo Base of Schizo CSR Base
*/
/*
* The following macro defines the 42-bit bus width support for SAFARI bus
* and JBUS in DVMA and iommu bypass transfers:
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCISCH_H */