/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCIPSY_H
#define _SYS_PCIPSY_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Performance counters information.
*/
#define PSYCHO_SHIFT_PIC1 0
/*
* Psycho-specific register offsets & bit field positions.
*/
/*
* Offsets of global registers:
*/
/*
* psycho performance counters offsets.
*/
/*
* Offsets of registers in the interrupt block:
*/
/*
* Offsets of registers in the PBM block:
*/
/*
* Offsets of registers in the streaming cache block:
*/
/*
* Address space offsets and sizes:
*/
/*
* psycho control register bit definitions:
*/
/*
* psycho ECC UE AFSR bit definitions:
*/
/*
* psycho ECC CE AFSR bit definitions:
*/
/*
* psycho pci control register bits:
*/
/*
* psycho PCI asynchronous fault status register bit definitions:
*/
/*
* psycho PCI diagnostic register bit definitions:
*/
/*
* for sabre
*/
/*
* The following macro defines the 40-bit bus width support for UPA bus
* in DVMA and iommu bypass transfers:
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCIPSY_H */