29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER START
29949e866e40b95795203f3ee46f44a197c946e4stevel * The contents of this file are subject to the terms of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * Common Development and Distribution License (the "License").
29949e866e40b95795203f3ee46f44a197c946e4stevel * You may not use this file except in compliance with the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
29949e866e40b95795203f3ee46f44a197c946e4stevel * See the License for the specific language governing permissions
29949e866e40b95795203f3ee46f44a197c946e4stevel * and limitations under the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * When distributing Covered Code, include this CDDL HEADER in each
29949e866e40b95795203f3ee46f44a197c946e4stevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
29949e866e40b95795203f3ee46f44a197c946e4stevel * If applicable, add the following below this CDDL HEADER, with the
29949e866e40b95795203f3ee46f44a197c946e4stevel * fields enclosed by brackets "[]" replaced with your own identifying
29949e866e40b95795203f3ee46f44a197c946e4stevel * information: Portions Copyright [yyyy] [name of copyright owner]
29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER END
29949e866e40b95795203f3ee46f44a197c946e4stevel * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Use is subject to license terms.
29949e866e40b95795203f3ee46f44a197c946e4stevel#pragma ident "%Z%%M% %I% %E% SMI"
29949e866e40b95795203f3ee46f44a197c946e4stevelextern "C" {
29949e866e40b95795203f3ee46f44a197c946e4stevel * Debugging macros
29949e866e40b95795203f3ee46f44a197c946e4stevel * The DPRINTF macro can be used by setting the sysc_debug_print_level to the
29949e866e40b95795203f3ee46f44a197c946e4stevel * appropriate debugging level. The debug levels are defined in each source
29949e866e40b95795203f3ee46f44a197c946e4stevel * file where this header file is included. The scoping of sysc_debug_info,
29949e866e40b95795203f3ee46f44a197c946e4stevel * and sysc_debug_print_level is to the file which included the header file.
29949e866e40b95795203f3ee46f44a197c946e4stevel * If multiple levels need to be output, the values can be 'ored'
29949e866e40b95795203f3ee46f44a197c946e4stevel * together into sysc_debug_print_level. If sysc_debug_print_line's bit 1 is
29949e866e40b95795203f3ee46f44a197c946e4stevel * set, the line number of the debugging statement is printed out. If it has
29949e866e40b95795203f3ee46f44a197c946e4stevel * bit 2 set, the macro will drop into either the debugger or the OBP PROM.
29949e866e40b95795203f3ee46f44a197c946e4stevelextern void debug_enter(char *);
29949e866e40b95795203f3ee46f44a197c946e4stevel#define _PRINTF prom_printf /* For logging to the console */
29949e866e40b95795203f3ee46f44a197c946e4stevel if (sysc_debug_print_level & (print_flag) && sysc_debug_info & \
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* DEBUG */
29949e866e40b95795203f3ee46f44a197c946e4stevel * OBP supplies us with 3 register sets for the clock-board node. The code for
29949e866e40b95795203f3ee46f44a197c946e4stevel * the syctrl driver relies on these register sets being presented by the
29949e866e40b95795203f3ee46f44a197c946e4stevel * PROM in the order specified below. If this changes, the following comments
29949e866e40b95795203f3ee46f44a197c946e4stevel * must be revised and the code in sysctrl_attach() must be changed to reflect
29949e866e40b95795203f3ee46f44a197c946e4stevel * these revisions.
29949e866e40b95795203f3ee46f44a197c946e4stevel * They are:
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0 Clock frequency registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * 1 Misc registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * 2 Clock version register
29949e866e40b95795203f3ee46f44a197c946e4stevel * The offsets are defined as offsets in bytes from the base of the OBP
29949e866e40b95795203f3ee46f44a197c946e4stevel * register to which the register belongs to.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Register set 0 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_CLK_FREQ2 0x2 /* offset of clock register 2 */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Important bits for Clock Frequency register 2 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define RCONS_UART_EN 0x80 /* Remote console reset enabled */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define GEN_RESET_EN 0x40 /* Enable reset on freq change */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TOD_RESET_EN 0x20 /* Enable reset from TOD watchdog */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_DIV_0 0x02 /* Cpu module divisor bit 0 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_RANGE 0x0c /* Bits 3:2 control the clock range */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_DIV_1 0x10 /* Cpu module divisor bit 1 */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Register set 1 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_CTRL 0x0 /* Offset of System Control register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_STAT1 0x10 /* Offset of System Status1 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_STAT2 0x20 /* Offset of System Status2 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_PSSTAT 0x30 /* Offset of Power Supply Status */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_PSPRES 0x40 /* Offset of Power Supply Presence */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_TEMP 0x50 /* Offset of temperature register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_DIAG 0x60 /* Offset of interrupt diag register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_OFF_PPPSR 0x70 /* Offset of second Power Supply Status */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_STATUS1_PADDR 0x1fff8906010 /* physical address for physio */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Register set 2 (not present on old vintage clock boards) */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLK_VERSION_REG 0x0 /* Offset of clock version register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLK_VERSION_REG_PADDR 0x1fff890c000 /* physical address for physio */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Important bits for the board version register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define RMT_CONS_OFFSET 0x4004 /* Offset of Remote Console UART */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define RMT_CONS_LEN 0x8 /* Size of Remote Console UART */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for System Control register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_PPS_FAN_FAIL_EN 0x80 /* PPS Fan Fail Interrupt Enable */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_PS_FAIL_EN 0x40 /* PS DC Fail Interrupt Enable */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_AC_PWR_FAIL_EN 0x20 /* AC Power Fail Interrupt Enable */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_SBRD_PRES_EN 0x10 /* Board Insertion Interrupt En */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_PWR_OFF 0x08 /* Bit to turn system power */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_LED_LEFT 0x04 /* System Left LED. Reverse Logic */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for System Status1 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_SECURE 0x20 /* ==0 Keyswitch in secure pos. */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_P_FAN_PRES 0x10 /* ==0 PPS cooling tray present */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_BRD_PRES 0x08 /* ==0 When board inserted */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_PPS0_PRES 0x04 /* ==0 If PPS0 present */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_TOD_NOT_RST 0x02 /* ==0 if TOD reset occurred */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_GEN_NOT_RST 0x01 /* ==0 if clock freq reset occured */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macros to determine system type from System Status1 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for Clock Version Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_PLUS_SYSTEM 0x00 /* bit 7 is low for plus system */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macros to determine frequency capability from clock version register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macros to determine system type based on number of physical slots */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for System Status2 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_RMTE_NOT_RST 0x80 /* Remote Console reset occurred */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_CLK_33_OK 0x20 /* 3.3V OK on clock board */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_CLK_50_OK 0x10 /* 5.0V OK on clock board */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_AC_FAIL 0x08 /* System lost AC Power source */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_RACK_FANFAIL 0x04 /* Peripheral Rack fan status */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_AC_FAN_OK 0x02 /* Status of 4 AC box fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_KEYSW_FAN_OK 0x01 /* Status of keyswitch fan */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for Power Supply Presence register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_PPS1_PRES 0x80 /* ==0 if PPS1 present in 4slot */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for Precharge and Peripheral Power Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_NOT_CURRENT_S 0x80 /* Current share backplane */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_V5_P_PCH_OK 0x08 /* ==1 peripheral 5v precharge ok */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_V12_P_PCH_OK 0x04 /* ==1 peripheral 12v precharge ok */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_V3_PCH_OK 0x02 /* ==1 system 3.3v precharge ok */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_V5_PCH_OK 0x01 /* ==1 system 5.0v precharge ok */
29949e866e40b95795203f3ee46f44a197c946e4stevel * The Power Supply shadow kstat is too large to fit in a kstat_named
29949e866e40b95795203f3ee46f44a197c946e4stevel * struct, so it has been changed to be a raw kstat.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* States of a power supply DC voltage. */
29949e866e40b95795203f3ee46f44a197c946e4stevelenum e_state { PS_BOOT = 0, PS_OUT, PS_UNKNOWN, PS_OK, PS_FAIL };
29949e866e40b95795203f3ee46f44a197c946e4stevelenum e_pres_state { PRES_UNKNOWN = 0, PRES_IN, PRES_OUT };
29949e866e40b95795203f3ee46f44a197c946e4stevel * several power supplies are managed -- 8 core power supplies,
29949e866e40b95795203f3ee46f44a197c946e4stevel * up to two pps, a couple of clock board powers and a register worth
29949e866e40b95795203f3ee46f44a197c946e4stevel * of precharges.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* core PS 0 thru 7 are index 0 thru 7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYS_P_FAN_INDEX 18 /* the peripheral fan assy */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* fan timeout structures */
29949e866e40b95795203f3ee46f44a197c946e4stevel * States of the secure key switch position.
29949e866e40b95795203f3ee46f44a197c946e4stevelenum keyswitch_state { KEY_BOOT = 0, KEY_SECURE, KEY_NOT_SECURE };
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Redundant power states */
29949e866e40b95795203f3ee46f44a197c946e4stevelenum power_state { BOOT = 0, BELOW_MINIMUM, MINIMUM, REDUNDANT };
29949e866e40b95795203f3ee46f44a197c946e4stevel * minor device mask
29949e866e40b95795203f3ee46f44a197c946e4stevel * B - bottom 4 bits (16 slots) are for the slot/receptacle id
29949e866e40b95795203f3ee46f44a197c946e4stevel * I - next 4 bits are for the instance number
29949e866e40b95795203f3ee46f44a197c946e4stevel * X - rest are not used
29949e866e40b95795203f3ee46f44a197c946e4stevel * Upper Lower
29949e866e40b95795203f3ee46f44a197c946e4stevel * XXXXX...............IIIIBBBB
29949e866e40b95795203f3ee46f44a197c946e4stevel * device at instance 0 and slot 8, minor device number 0x8 = decimal 8
29949e866e40b95795203f3ee46f44a197c946e4stevel * device at instance 1 and slot 10, minor device number 0x1A = decimal 26
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macro definitions */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define GETSLOT(unit) (getminor(unit) & SYSC_SLOT_MASK)
29949e866e40b95795203f3ee46f44a197c946e4stevel ((getminor(unit) & SYSC_INSTANCE_MASK) >> SYSC_INSTANCE_SHIFT)
29949e866e40b95795203f3ee46f44a197c946e4stevel (((inst) << SYSC_INSTANCE_SHIFT) & SYSC_INSTANCE_MASK)
29949e866e40b95795203f3ee46f44a197c946e4stevel ((struct sysctrl_soft_state *)ddi_get_soft_state(sysctrlp, getminor(i)))
29949e866e40b95795203f3ee46f44a197c946e4stevel * Definition of sysctrl ioctls.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_FAIL_TIMEOUT_USEC (500 * (MICROSEC / MILLISEC))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define BRD_INSERT_DELAY_USEC (500 * (MICROSEC / MILLISEC))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define BLINK_LED_TIMEOUT_USEC (300 * (MICROSEC / MILLISEC))
29949e866e40b95795203f3ee46f44a197c946e4stevel * how many ticks to wait to register the state change
29949e866e40b95795203f3ee46f44a197c946e4stevel * NOTE: ticks are measured in PS_FAIL_TIMEOUT_USEC clicks
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Note: this timeout needs to be longer than FAN_OK_TIMEOUT_USEC */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* NOTE: these ticks are measured in PPS_FAN_TIMEOUT_USEC clicks */
29949e866e40b95795203f3ee46f44a197c946e4stevel * how many spurious interrupts to take during a SPUR_LONG_TIMEOUT_USEC
29949e866e40b95795203f3ee46f44a197c946e4stevel * before complaining
29949e866e40b95795203f3ee46f44a197c946e4stevel * Global driver structure which defines the presence and status of
29949e866e40b95795203f3ee46f44a197c946e4stevel * all board power supplies.
29949e866e40b95795203f3ee46f44a197c946e4stevel enum e_pres_state pshadow; /* presense shadow state */
29949e866e40b95795203f3ee46f44a197c946e4stevel * for sysctrl_thread_wakeup()
29949e866e40b95795203f3ee46f44a197c946e4stevel * Structures used in the driver to manage the hardware
29949e866e40b95795203f3ee46f44a197c946e4stevel * XXX will need to add a nodeid
29949e866e40b95795203f3ee46f44a197c946e4stevel pnode_t options_nodeid; /* for nvram powerfail-time */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t iblock; /* High level interrupt cookie */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_idevice_cookie_t idevice; /* TODO - Do we need this? */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t spur_id; /* when we get a spurious int... */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t spur_int_c; /* spur int cookie */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t spur_high_id; /* when we reenable disabled ints */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t spur_long_to_id; /* long timeout softint */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t ac_fail_high_id; /* ac fail re-enable softintr id */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t ps_fail_int_id; /* ps fail from intr softintr id */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t ps_fail_c; /* ps fail softintr cookie */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t ps_fail_poll_id; /* ps fail from polling softintr */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t pps_fan_id; /* pps fan fail softintr id */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t pps_fan_high_id; /* pps fan re-enable softintr id */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t sbrd_gone_id; /* sbrd removed softintr id */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_softintr_t blink_led_id; /* led blinker softint */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t sys_led_c; /* mutex cookie for sys LED lock */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *clk_freq1; /* Clock frequency reg. 1 */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *clk_freq2; /* Clock frequency reg. 2 */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *status1; /* System Status1 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *status2; /* System Status2 register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *ps_stat; /* Power Supply Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *ps_pres; /* Power Supply Presence register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *pppsr; /* 2nd Power Supply Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *temp_reg; /* VA of temperature register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *rcons_ctl; /* VA of Remote console UART */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uchar_t *clk_ver; /* clock version register */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* This mutex protects the following data */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* NOTE: *csr should only be accessed from interrupt level */
29949e866e40b95795203f3ee46f44a197c946e4stevel kmutex_t csr_mutex; /* locking for csr enable bits */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t pps_fan_saved; /* cached pps fanfail state */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* This mutex protects the following data */
29949e866e40b95795203f3ee46f44a197c946e4stevel kmutex_t spur_int_lock; /* lock spurious interrupt data */
29949e866e40b95795203f3ee46f44a197c946e4stevel timeout_id_t spur_timeout_id; /* quiet the int timeout id */
29949e866e40b95795203f3ee46f44a197c946e4stevel timeout_id_t spur_long_timeout_id; /* spurious long timeout interval */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* This mutex protects the following data */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct ps_state ps_stats[SYS_PS_COUNT]; /* state struct for all ps */
29949e866e40b95795203f3ee46f44a197c946e4stevel enum power_state power_state; /* redundant power state */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* This mutex protects the following data */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* various elements protected by their inherent access patterns */
29949e866e40b95795203f3ee46f44a197c946e4stevel int pps_fan_external_state; /* external state of the pps fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel int pps_fan_state_count[SYS_PPS_FAN_COUNT]; /* fan state counter */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct temp_stats tempstat; /* in memory storage of temperature */
29949e866e40b95795203f3ee46f44a197c946e4stevel enum keyswitch_state key_shadow; /* external state of the key switch */
29949e866e40b95795203f3ee46f44a197c946e4stevel int enable_rcons_atboot; /* enable remote console at boot */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Kstat structures used to contain data which is requested by user
29949e866e40b95795203f3ee46f44a197c946e4stevel * programs.
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named csr; /* system control register */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named fan_status; /* shadow status 2 for fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named key_status; /* shadow status for key */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named power_state; /* redundant power status */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named clk_ver; /* clock version register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYSC_ERR_SET(pkt, err) (pkt)->cmd_cfga.errtype = (err)
29949e866e40b95795203f3ee46f44a197c946e4stevel * Function prototype
29949e866e40b95795203f3ee46f44a197c946e4stevelint sysc_policy_disconnect(struct sysctrl_soft_state *,
29949e866e40b95795203f3ee46f44a197c946e4stevelint sysc_policy_unconfigure(struct sysctrl_soft_state *,
29949e866e40b95795203f3ee46f44a197c946e4stevelint sysc_policy_configure(struct sysctrl_soft_state *,
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid sysc_policy_update(void *softsp, sysc_cfga_stat_t *sc, sysc_evt_t event);
29949e866e40b95795203f3ee46f44a197c946e4stevelextern void sysctrl_suspend_prepare(void);
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _KERNEL */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _ASM */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _SYS_SYSCTRL_H */