/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2002 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_AXQ_H
#define _SYS_AXQ_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* AXQ register offset constant */
/*
* AXQ system register offsets
* Each Starcat AXQ asic instance is logically
* associated with each slot in the expander board.
* Slot 0 is the full slot (or full bandwidth slot)
* and Slot1 is the half slot (or half bandwidth slot).
* Some system registers are only accessible in certain
* slot type.
*/
/* domain control register (slot0 & slot1) */
/* cpu2ssc intr register */
/* performance counters (one set per slot) */
/* CASM slots (for both slot0 & slot1) */
/* CDC registers (only available in slot0) */
/* NASM registers */
#define AXQ_NASM_TYPE_IO 0
/* SDI Timeout register */
/*
* Bits for domain control register
*/
/*
* Bits for CDC registers
*/
/* CDC control test register */
/* CDC Address Test register */
/* CDC counter test register */
/*
* Bits for CPU to SSC interrupt register
*/
/*
* Each AXQ instance has one pcr (performance control
* register) controlling 3 pics (performance instru-
* mentation counter). pic0 and pic1 are similar
* and have identical inputs to their muxes. pic2
* only counts the clock.
*/
/* Bit masks for selecting pic mux input */
/* Shift definitions into pcr for programming pics */
/* event constants */
/* AXQ constants */
#define SLOT0_AXQ 0
/*
* Struct element describing a eventname and
* its pcr-mask.
*/
typedef struct axq_event_mask {
char *event_name;
/*
* NASM RAM system register for reading
*/
typedef union {
struct axq_nasm_read {
} bit;
/*
* NASM RAM system register for reading
*/
typedef union {
struct axq_nasm_write {
} bit;
/*
* Global data structure that is used to
* export certain axq registers in
* local space. Right now, the only
* register we want to access in local space
* is the cheetah2ssc interrupt reg. There
* could be more in future.
*/
struct axq_local_regs {
int initflag;
};
/*
* axq soft state data structure.
*/
struct axq_soft_state {
/* CASM register slots */
/* NASM register */
/* CDC registers (only in slot0) */
/* performance counters */
/* SDI timeout register */
#ifndef _AXQ_LOCAL_ACCESS_SUPPORTED
/*
* No local access for cpu2ssc intr
* Need to provide per instance explicit expander addressing
*/
#endif /* _AXQ_LOCAL_ACCESS_SUPPORTED */
};
/*
* Public interface
*/
extern int axq_cdc_flush(uint32_t, int, int);
extern int axq_cdc_flush_all();
extern int axq_cdc_disable_flush_all();
extern void axq_cdc_enable_all();
extern int axq_iopause_enable_all(uint32_t *);
extern void axq_iopause_disable_all();
extern int axq_casm_write_all(int, uint32_t);
extern int axq_do_casm_rename_script(uint64_t **, int, int);
extern int axq_cpu2ssc_intr(uint8_t);
extern void axq_array_rw_enter(void);
extern void axq_array_rw_exit(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYS_AXQ_H */