/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2001 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _MONTECARLO_SYS_SCSB_H
#define _MONTECARLO_SYS_SCSB_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _KERNEL
#include <sys/inttypes.h>
#endif /* _KERNEL */
/*
* CPU and AlarmCard slots
* MonteCarlo: CPU = SLOT1, AC = SLOT8
* Tonga: CPU = SLOT3, AC = SLOT1
*/
/*
* SCSB operations between scsb and the hotswap controller module
*/
/*
* SCSB_HSC_AC_GET_SLOT_INFO for hsc_ac_op()
* to return hsc_slot_t pointer (for debugging)
*/
/*
* The register set starting address, and macro for translating
* the index to 0 base.
*/
/*
* ----------------------
* P1.0
* ----------------------
* The following three register offset groups are defined for P1.0 where
* FRUs might have three different bit offset values,
* Group 1: LEDs, Slot Reset, and BrdHlthy,
*/
#define REG_GROUP1 0
/*
* ----------------------
* P1.5
* ----------------------
* The table access macros use BASE register plus register offset to get the
* correct register index or address.
* The SCB FRU type has two register offsets, LED reg and INT reg offsets.
* The one in fru_offsets[] is for the NOK, OK, and BLINK LED data.
* To get the register offset for the INTSRC and INTMASK registers, the
* following constant must be added to the table value returned by
* FRU_REG_INDEX(SCTRL_EVENT_SCB, SCTRL_INTMSK_BASE), NOT SCTRL_INTMASK_BASE.
* Given enough time, this too should be handled via macro access to tables.
*/
/*
* ----------------------------------
* P0.6, P1.0, P1.5, P2.0 DEFINITIONS
* ----------------------------------
*/
/*
* SCB Register Indicies to scb_reg_index[] table
*/
#define SCTRL_SYS_CMD_BASE 0
/*
* The last two definitions are for register offset compatibility.
* These will be used with FRU_REG_INDEX macros, for P1.0 and P1.5, so 1.5
* register offsets in upper nibble of fru_offset[] tables will be consistent.
* This happens because the HLTHY INTs and INT masks come before the slots and
* FRUs. That's what changes the register offsets.
* The only EXCEPTION is the ALARM RESET register, which for P1.5 is not
* BASE + 3 as in all other cases, but BASE + 1. FRU_REG_INDEX(code,base) does
* NOT work for ALARM RESET. Use ALARM_RESET_REG_INDEX() instead.
* FRU_REG_INDEX() works differently for P1.0, using offset groups to calculate
* the index to the fru_offset[] table.
*/
/*
* REGISTER BIT OFFSETS
* For the bit definitions, the SCB register sets are divided into two tables,
* 1. scb_1x_fru_offset[] bit-offsets for all FRUs and
* Interrupt events
* and any remaining bits, like MPID.
*
* This is a bit historic from P0.6,P1.0 days.
* The fru_offset table is indexed using the SCTRL_EVENT_ codes defined in
* mct_topology.h. Almost all of these describe interrupt generated events.
* Ths sys_offset table contains anything else, mostly the System Control
*/
/*
* scb_1x_sys_offset[] table indicies
*
*/
#define SCTRL_SYS_PS1_OFF 0
/*
*/
/*
* SCB Identity register offsets
*/
/* numregs table order and indicies */
#define SCTRL_SYS_CMD_NUM 0
/*
* Macro Definitions for register and bit offset values
*/
/* macros names for scb_numregs[] access */
/*
* Maximum number of registers in a register group
* Needed for above register groups array sizing
*/
REG_GROUP2))))
& 0xf) + rx)
& 0xf) + rx)
& 0xf)) + rx)
/*LINTED table used in scsb.o and system utilities*/
/*LINTED table used in scsb.o and system utilities*/
/*LINTED table used in scsb.o and system utilities*/
/*LINTED table used in scsb.o and system utilities*/
/*
* --------------------
* Common TABLES
* --------------------
*/
/*
* FRU type to unit 1 event_code, see FRU_UNIT_TO_EVCODE() macro above.
* Table order is dependent on scsb_utype_t definition in mct_topology.h
*/
/*LINTED table used in scsb.o and system utilities*/
};
/*
* --------------------
* P0.6 and P1.0 TABLES
* --------------------
*/
/*
* MonteCarlo: Programming Inteface Specifications Version 0.9
* 10/27/99
* NOTE: P0.6 FANs and PDUs were different
*/
/*LINTED table used in scsb.o and system utilities*/
0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, /* 00 - 07 */
0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, /* 08 - 15 */
0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, /* 16 - 23 */
0xD8, 0xD9, 0xDA, 0xDB, 0x00, 0x00, 0xDC, 0x00, /* 24 - 31 */
0xDC, 0xDD, 0xDE, 0xDF, 0xD8, 0xDC, 0x00, 0x00, /* 32 - 39 */
};
/*LINTED table used in scsb.o and system utilities*/
2, 4, 4, 8, 2, 2, 1, 2, 6, 4, 4, 32
};
/*
* MCT_MAX_FRUS * REG_GROUPS_NUM
*
* FRU order:
* 0 - 9: Slots 1 - 10
* 10 - 11: PDU 1 - 2
* 12 - 13: PS 1 - 2
* 14 - 16: Disk 1 - 3
* 17 - 19: Fan 1 - 3
* 20: Alarm Card
* 21: SCB
* 22: SSB
* 23: CRTM
* 24: CFTM
* 25: PRTM
* 26: PWRDWN
* 27: REPLACE
* 28: ALARM_INT
* 29 - 31: Unused
*
* A register base group offset is added to the register base value to
* find the index into the reg_index table.
* Example: LED_NOK_BASE + '1' = register for slots 7-10 NOK LEDs
* This offset is encoded in the upper nibble in the following table
* The register base group definitions are:
* base group offset group
* ---------------------- ------------
* SCTRL_LED_NOK_BASE G1
* SCTRL_LED_OK_BASE G1
* SCTRL_RESET_BASE G1
* SCTRL_BLINK_OK_BASE G1
* SCTRL_BHLTHY_BASE G1
* SCTRL_SYSCFG_BASE G2
* SCTRL_INTSRC_BASE G3
* SCTRL_INTMASK_BASE G3
* SCTRL_SYS_CMD_BASE G4
*
* See FRU_OFFSET() macro
*/
/*LINTED table used in scsb.o and system utilities*/
/* Register Group 1 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
0x10, 0x11, 0x12, 0x13, /* SLOT 7-10 */
0x23, 0x24, 0x25, /* Disks 1-3 */
0x33, 0x34, 0x35, /* Fans 1-3 */
0xFF, 0x20, 0xFF, /* Alarm Card, SCB, SSB */
0xFF, 0xFF, 0xFF, /* CRTM, CFTM, PRTM */
0xFF, 0xFF, 0xFF, /* PWRDWN, SCBRR, ACINT */
0xFF, 0xFF, 0xFF, /* Unused */
/* Register Group 2 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
0x10, 0x11, 0x12, 0x13, /* SLOT 7-10 */
0x40, 0x41, 0x42, /* Disks 1-3 */
0x32, 0x33, 0x34, /* Fans 1-3 */
0x50, 0xFF, 0x35, /* Alarm Card, SCB, SSB */
0x43, 0x44, 0x45, /* CRTM, CFTM, PRTM */
0xFF, 0xFF, 0xFF, /* PWRDWN, SCBRR, ACINT */
0x24, 0x26, 0x20, /* STAT0, STAT1, MPID0 */
/* Register Group 3 */
0x31, 0x32, 0x33, 0x34, 0x35, 0x36, /* SLOT 1-6 */
0x37, 0x26, 0x27, 0x16, /* SLOT 7-10 */
0x20, 0x21, 0x22, /* Disks 1-3 */
0x12, 0x13, 0x14, /* Fans 1-3 */
0x30, 0x04, 0x15, /* Alarm Card, SCB, SSB */
0x23, 0x24, 0x25, /* CRTM, CFTM, PRTM */
0x00, 0x02, 0x03, /* PWRDWN, SCBRR, ACINT */
0xFF, 0xFF, 0xFF, /* Unused */
};
/*LINTED table used in scsb.o and system utilities*/
0x00, 0x01, 0x06, 0x07, 0x10, 0x11, 0x12, 0x13,
0x15, 0x16, 0xFF, 0x02, 0x03, 0x04, 0x05, 0x14,
0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x00, 0x07,
};
/*LINTED table used in scsb.o and system utilities*/
0x11, 0x2F, 0x3F, 0xFF, 0x00, 0x00,
};
/*
* --------------------
* P1.5 and P2.0 TABLES
* --------------------
*/
/*
* MonteCarlo: Programming Inteface Specifications
* Chapter 12 from the MonteCarlo System Specification
* 02/08/00: Chapter update from Carl Meert
*/
/*LINTED table used in scsb.o and system utilities*/
0xE0, 0xE1, 0xC0, 0xC1, 0xC2, 0xC2, 0xC3, 0xC4, /* 00 - 07 */
0xC5, 0xC5, 0xE2, 0xE3, 0xC6, 0xC7, 0xC8, 0xCF, /* 08 - 15 */
0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0x00, 0x00, /* 16 - 23 */
0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, /* 24 - 31 */
0xD8, 0xD9, 0xDA, 0xDB, 0xD2, 0xD8, 0x00, 0x00, /* 32 - 39 */
};
/*LINTED table used in scsb.o and system utilities*/
2, 3, 3, 6, 2, 3, 1, 2, 4, 6, 6, 48
};
/*LINTED table used in scsb.o and system utilities*/
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
0x06, 0x07, 0x16, 0x17, /* SLOT 7-10 */
0x23, 0x24, 0x25, /* Disks 1-3 */
0x20, 0x21, 0xFF, /* Fans 1-3 */
0x30, 0x15, 0x33, /* Alarm Card, SCB, SSB */
0x31, 0x14, 0x32, /* CRTM, CFTM, PRTM */
0x34, 0xFF, 0x36, /* PWRDWN, SCBRR, ACINT */
0xFF, 0xFF, 0xFF, /* Unused */
};
/*LINTED table used in scsb.o and system utilities*/
0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
0x14, 0x15, 0x16, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x34, 0x35, 0x36, 0x37, 0x10, 0x12, 0x00, 0x07
};
/*LINTED table used in scsb.o and system utilities*/
0xFF, 0x00, 0xFF, 0x1A, 0xFB, 0x7F,
};
/*
* scsb_state values
* outside _KERNEL for smctrl test utility
*/
#ifdef _KERNEL
/*
* The System Controller Board uses the Xilinx to control the I2C bus.
* The address should really go to scsb.conf file.
* The I2C address of the System Controller Board
*/
/*
* definitions for Interrupt Event Code handling
*/
/*
* return values for check_event_procs()
*/
/*
* scsb_queue_ops() definitions
* Operations:
*/
/*
* Return values:
* 0 - 15 are valid clone numbers used as index to clone_devs[]
* and returned for some operations instead of QOP_OK.
*/
/*
* minor_t definitions
* bits 2-0 SCB instance 0-7
* bit 3 Clone device for sm_open()
* bits 7-4 Cloned device numbers for a total of 15: 0x1# - 0xf#
* Must start with '1' to avoid conflict with:
* 0x00 non-clone device node for instance 0
* 0x08 the clone device node for instance 0
* the new minor_t for the clone is all of the above.
*/
typedef struct clone_dev {
} clone_dev_t;
typedef struct {
} scsb_state_t;
#if defined(DEBUG)
extern void prom_printf(const char *, ...);
scsb_debug_prnt(fmt, 0, 0, 0, 0, 0);
#else
#endif
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _MONTECARLO_SYS_SCSB_H */