px_lib4u.h revision 269473047d747f7815af570197e4ef7322d3632c
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PX_LIB4U_H
#define _SYS_PX_LIB4U_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Errors returned.
*/
#define H_EOK 0 /* Successful return */
/* no translation exists */
/*
* Register base definitions.
*
* The specific numeric values for CSR, XBUS, Configuration,
* Interrupt blocks and other register bases.
*/
typedef enum {
PX_REG_CSR = 0,
/*
*
* SUN4U px specific data structure.
*/
/* Control block soft state structure */
typedef struct px_cb_list {
struct px_cb_list *next;
} px_cb_list_t;
/* IO chip type */
typedef enum {
PX_CHIP_UNIDENTIFIED = 0,
PX_CHIP_FIRE = 1,
PX_CHIP_OBERON = 2
typedef struct px_cb {
int attachcnt; /* number of attached px */
} px_cb_t;
typedef struct pxu {
void *msiq_mapped_p;
/* sun4u specific vars */
/* PCItool */
} pxu_t;
/* cpr_flag */
#define PX_NOT_CPR 0
#define PX_ENTERED_CPR 1
/*
* Event Queue data structure.
*/
typedef struct eq_rec {
} eq_rec_t;
/*
* EQ record type
*
* Upper 4 bits of eq_rec_fmt_type is used
* to identify the EQ record type.
*/
/* EQ State */
/*
* Default EQ Configurations
*/
#define EQ_CNT 36
#define EQ_REC_CNT 128
#define EQ_1ST_ID 0
#define EQ_1ST_DEVINO 24
#define MMU_INVALID_TTE 0ull
#define MMU_OBERON_PADDR_MASK 0x7fffffffffff
#define MMU_FIRE_PADDR_MASK 0x7ffffffffff
/*
* control register decoding
*/
/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
/*
* For Fire mmu bypass addresses, bit 43 specifies cacheability.
*/
/*
* For Oberon mmu bypass addresses, bit 47 specifies cacheability.
*/
/*
* The following macros define the address ranges supported for DVMA
* and mmu bypass transfers. For Oberon, bit 63 is used for ordering.
*/
#define MMU_FIRE_BYPASS_BASE 0xFFFC000000000000ull
#define MMU_FIRE_BYPASS_END 0xFFFC03FFFFFFFFFFull
#define MMU_OBERON_BYPASS_BASE 0x7FFC000000000000ull
#define MMU_OBERON_BYPASS_END 0x7FFC7FFFFFFFFFFFull
#define MMU_OBERON_BYPASS_RO 0x8000000000000000ull
#define MMU_TSB_PA_MASK 0x7FFFFFFFE000
/*
* The following macros are for loading and unloading io tte
* entries.
*/
#define MMU_TTE_SIZE 8
/* Interrupt states */
#define INTERRUPT_IDLE_STATE 0
#define INTERRUPT_RECEIVED_STATE 1
#define INTERRUPT_PENDING_STATE 3
/*
* Defines for link width and max packet size for ACKBAK Latency Threshold Timer
* and TxLink Replay Timer Latency Table array sizes
* Num Link Width Packet Size
* 0 1 128
* 1 4 256
* 2 8 512
* 3 16 1024
* 4 - 2048
* 5 - 4096
*/
#define LINK_WIDTH_ARR_SIZE 4
#define LINK_MAX_PKT_ARR_SIZE 6
/*
* Defines for registers which have multi-bit fields.
*/
#define TLU_LINK_CONTROL_ASPM_DISABLED 0x0
#define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1
#define TLU_LINK_CONTROL_ASPM_L1_EN 0x2
#define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3
#define TLU_CONTROL_CONFIG_DEFAULT 0x1
#define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull
#define TLU_CONTROL_MPS_MASK 0x1C
#define TLU_CONTROL_MPS_SHIFT 2
#define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0
#define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1
#define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2
#define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3
#define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull
#define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull
#define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF
#define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2
#define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5
#define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0
#define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120
#define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2
#define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c
/* LPU LTSSM states */
#define LPU_LTSSM_L0 0x0
#define LPU_LTSSM_L1_IDLE 0x15
/* TLU Control register bits */
#define TLU_REMAIN_DETECT_QUIET 8
/* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */
#define PX_PA_BDF_SHIFT 12
/*
* Fire hardware specific version definitions.
* All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20
*/
#define FIRE_MOD_REV_20 0x03
/*
* Oberon specific definitions.
*/
#define OBERON_RANGE_PROP_MASK 0x7fff
/*
* HW specific paddr mask.
*/
extern uint64_t px_paddr_mask;
int flags);
/*
* MSIQ Functions:
*/
/*
* MSI Functions:
*/
/*
* MSG Functions:
*/
/*
*/
/*
* Hotplug functions:
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PX_LIB4U_H */