/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* CPU functions to the Safari Configurator (gptwo_cpu)
*/
#include <sys/autoconf.h>
#include <sys/ndi_impldefs.h>
#include <sys/ddi_impldefs.h>
#include <sys/machsystm.h>
#include <sys/gptwo_cpu.h>
#include <sys/cheetahregs.h>
#ifdef DEBUG
int gptwo_cpu_debug = 0;
if (gptwo_cpu_debug >= level) \
#else
#endif
/*
* Devinfo branch create arg
*/
struct bca {
};
/*
* Module linkage information for the kernel.
*/
extern struct mod_ops mod_miscops;
&mod_miscops, /* Type of module */
"gptwo->cpu configurator",
};
};
int
_init(void)
{
int err = 0;
/* register device with the configurator */
"failed to load, error=%d\n", err);
} else {
"has been loaded.\n");
}
return (err);
}
int
_fini(void)
{
return (mod_remove(&modlinkage));
}
int
{
}
{
int nodes = 0;
int i, j = 0;
for (i = 0; i < AGENTS_PER_PORT; i++) {
}
switch (implementation) {
case CHEETAH_IMPL:
case CHEETAH_PLUS_IMPL:
case JAGUAR_IMPL:
case PANTHER_IMPL:
break;
default:
"skipping configure of portid=0x%x", implementation,
portid);
ASSERT(0);
return (NULL);
}
if (CPU_IMPL_IS_CMP(implementation)) {
nodes++;
else
return (NULL);
}
for (i = 0; i < AGENTS_PER_PORT; i++) {
continue;
implementation)) {
/*
* If the CPU is a CMP, the entire branch is
* manipulated using just the top node. Thus,
* the dips of the individual cores do not need
* to be held or stored in the new node list.
*/
if (cmp_node) {
} else {
nodes++;
}
}
}
/* current implementations have 1 MC node per Safari port */
nodes++;
j = 0;
for (i = 0; i < AGENTS_PER_PORT; i++) {
}
if (cmp_node)
return (new_nodes);
}
static dev_info_t *
{
b.type = DEVI_BRANCH_SID;
return (NULL);
}
/*ARGSUSED*/
static int
{
"create name property\n");
return (DDI_WALK_ERROR);
}
"create portid property\n");
return (DDI_WALK_ERROR);
}
reg.gptwo_size_hi = 0;
sizeof (gptwo_regspec_t) / sizeof (int)) != DDI_SUCCESS) {
"create reg property\n");
return (DDI_WALK_ERROR);
}
return (DDI_WALK_TERMINATE);
}
static dev_info_t *
{
devi_branch_t b = {0};
b.type = DEVI_BRANCH_SID;
return (NULL);
}
/*ARGSUSED*/
static int
{
int rc;
return (DDI_WALK_ERROR);
switch (impl) {
case CHEETAH_IMPL:
case CHEETAH_PLUS_IMPL:
break;
case JAGUAR_IMPL:
case PANTHER_IMPL:
break;
default:
ASSERT(0);
return (DDI_WALK_ERROR);
}
return (rc);
}
/*
* Set properties common to cpu (non-CMP) and core (CMP) nodes.
*
* cpuid
* device_type
* manufacturer#
* implementation#
* mask#
* sparc-version
* clock-frequency
* #dtlb-entries
* #itlb-entries
*/
static int
{
"to create cpuid property\n");
return (DDI_WALK_ERROR);
}
"to create device_type property\n");
return (DDI_WALK_ERROR);
}
manufacturer) != DDI_SUCCESS) {
"to create manufacturer# property\n");
return (DDI_WALK_ERROR);
}
impl) != DDI_SUCCESS) {
"to create implementation# property\n");
return (DDI_WALK_ERROR);
}
mask) != DDI_SUCCESS) {
"to create mask# property\n");
return (DDI_WALK_ERROR);
}
"to create sparc-version property\n");
return (DDI_WALK_ERROR);
}
"to create clock-frequency property\n");
return (DDI_WALK_ERROR);
}
"to create #dtlb-entries property\n");
return (DDI_WALK_ERROR);
}
"to create #itlb-entries property\n");
return (DDI_WALK_ERROR);
}
return (DDI_WALK_CONTINUE);
}
/*
* Set cpu node properties for Cheetah and Cheetah+.
*
* name
* portid
* reg
* icache-size
* icache-line-size
* icache-associativity
* dcache-size
* dcache-line-size
* dcache-associativity
* ecache-size
* ecache-line-size
* ecache-associativity
*/
static int
{
char *node_name;
switch (impl) {
case CHEETAH_IMPL:
node_name = "SUNW,UltraSPARC-III";
break;
case CHEETAH_PLUS_IMPL:
/*
* Hard coding the ecache-associativity to 2 for Cheetah+.
* We probably should add this to the PCD.
*/
node_name = "SUNW,UltraSPARC-III+";
break;
default:
"implementation=0x%x\n", impl);
return (DDI_WALK_ERROR);
}
"to create name property\n");
return (DDI_WALK_ERROR);
}
"to create portid property\n");
return (DDI_WALK_ERROR);
}
reg.gptwo_size_hi = 0;
sizeof (gptwo_regspec_t) / sizeof (int)) != DDI_SUCCESS) {
"to create reg property\n");
return (DDI_WALK_ERROR);
}
"to create icache-size property\n");
return (DDI_WALK_ERROR);
}
"to create icache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create icache-associativity property\n");
return (DDI_WALK_ERROR);
}
"to create dcache-size property\n");
return (DDI_WALK_ERROR);
}
"to create dcache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create dcache-associativity property\n");
return (DDI_WALK_ERROR);
}
/*
* Get the External Cache Size from the Common PCD.
*/
"to create ecache-line-size property\n");
return (DDI_WALK_ERROR);
}
switch (ecache_size) {
case CH_ECACHE_1M_SIZE:
ecache_line_size = 64;
break;
case CH_ECACHE_4M_SIZE:
ecache_line_size = 256;
break;
case CH_ECACHE_8M_SIZE:
ecache_line_size = 512;
break;
default:
"ecache-size 0x%x\b", ecache_size);
return (DDI_WALK_ERROR);
}
"to create ecache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create ecache-associativity property\n");
return (DDI_WALK_ERROR);
}
/*
* Create the ecache-dimm-label property.
*/
dimms = 0;
(dimms < MAX_DIMMS_PER_PORT))
dimms++;
if (dimms) {
dimms);
}
return (DDI_WALK_TERMINATE);
}
/*
* Set cmp core node properties for Jaguar and Panther.
*
* name
* compatible
* reg
* l1-icache-size
* l1-icache-line-size
* l1-icache-associativity
* l1-dcache-size
* l1-dcache-line-size
* l1-dcache-associativity
* l2-cache-size
* l2-cache-line-size
* l2-cache-associativity
* l2-cache-sharing
* l3-cache-size
* l3-cache-line-size
* l3-cache-associativity
* l3-cache-sharing
*/
static int
{
char *compatible;
int dimms;
int i;
/*
* Get the External Cache Size from the Common PCD.
*/
switch (impl) {
case JAGUAR_IMPL:
compatible = "SUNW,UltraSPARC-IV";
/*
* Jaguar has no logical sharing of L2 cache, so the sharing
* bit-map will represent this core only.
*/
/*
* Jaguar has a split ecache, so the total ecache must be
* divided in half to get the ecache for the individual core.
*/
switch (l2_cache_size) {
case JG_ECACHE_4M_SIZE:
l2_cache_line_size = 64;
break;
case JG_ECACHE_8M_SIZE:
l2_cache_line_size = 128;
break;
default:
"invalid l2_cache-size 0x%x\n", l2_cache_size);
return (DDI_WALK_ERROR);
}
break;
case PANTHER_IMPL:
compatible = "SUNW,UltraSPARC-IV+";
/*
* For Panther, the L2 and L3 caches are logically shared by
* all enabled cores, so the sharing bit-map will represent
* all enabled cores. Panther split-mode is still considered
* shared.
*
* Check the PCD status to determine enabled cores.
*/
l2_cache_share = 0;
for (i = 0; i < AGENTS_PER_PORT; i++) {
l2_cache_share |= (1 << i);
}
}
break;
default:
"implementation=0x%x\n", impl);
return (DDI_WALK_ERROR);
}
"to create name property\n");
return (DDI_WALK_ERROR);
}
"to create compatible property\n");
return (DDI_WALK_ERROR);
}
"to create reg property\n");
return (DDI_WALK_ERROR);
}
"to create l1-icache-size property\n");
return (DDI_WALK_ERROR);
}
"to create icache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create l1-icache-associativity property\n");
return (DDI_WALK_ERROR);
}
"to create l1-dcache-size property\n");
return (DDI_WALK_ERROR);
}
"to create dcache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create l1-dcache-associativity property\n");
return (DDI_WALK_ERROR);
}
"to create l2-cache-size property\n");
return (DDI_WALK_ERROR);
}
"to create l2_cache-line-size property\n");
return (DDI_WALK_ERROR);
}
"to create l2-cache-associativity property\n");
return (DDI_WALK_ERROR);
}
"to create l2-cache-sharing property\n");
return (DDI_WALK_ERROR);
}
/*
* Create the ecache-dimm-label property.
*/
dimms = 0;
(dimms < MAX_DIMMS_PER_PORT))
dimms++;
if (dimms) {
dimms);
}
if (IS_PANTHER(impl)) {
"failed to create l3-cache-size property\n");
return (DDI_WALK_ERROR);
}
"failed to create l3-cache-line-size property\n");
return (DDI_WALK_ERROR);
}
"failed to create l3-cache-associativity "
"property\n");
return (DDI_WALK_ERROR);
}
"failed to create l3-cache-sharing property\n");
return (DDI_WALK_ERROR);
}
}
return (DDI_WALK_TERMINATE);
}
static dev_info_t *
{
devi_branch_t b = {0};
b.type = DEVI_BRANCH_SID;
return (NULL);
}
/*ARGSUSED*/
static int
{
"to create name property\n");
return (DDI_WALK_ERROR);
}
"to create compatible property\n");
return (DDI_WALK_ERROR);
}
"to create device_type property\n");
return (DDI_WALK_ERROR);
}
"to create portid property\n");
return (DDI_WALK_ERROR);
}
"to create cpuid property\n");
return (DDI_WALK_ERROR);
}
reg.gptwo_size_hi = 0;
sizeof (gptwo_regspec_t) / sizeof (int)) != DDI_SUCCESS) {
"to create reg property\n");
return (DDI_WALK_ERROR);
}
if (pcd->memory_layout) {
"to create memory-layout property\n");
return (DDI_WALK_ERROR);
}
}
/*
* Create the bank-status property.
*/
banks = 0;
(banks < MAX_BANKS_PER_PORT))
banks++;
if (banks) {
}
/*
* Create the dimm-status property.
*/
dimms = 0;
(dimms < MAX_DIMMS_PER_PORT))
dimms++;
if (dimms) {
}
return (DDI_WALK_TERMINATE);
}
/*ARGSUSED*/
static void
{
}
#ifdef DEBUG
static void
{
}
#endif