px_mmu.c revision 15e1afcd5e908ae29b1e6018838638befdc225a2
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * or http://www.opensolaris.org/os/licensing.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * PX mmu initialization and configuration
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/types.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/kmem.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/async.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/sysmacros.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/sunddi.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/ddi_impldefs.h>
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer#include <sys/vmem.h>
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer#include <sys/machsystm.h> /* lddphys() */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include <sys/iommutsb.h>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#include "px_obj.h"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsint
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qspx_mmu_attach(px_t *px_p)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs{
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs dev_info_t *dip = px_p->px_dip;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_mmu_t *mmu_p;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t tsb_i = 0;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs char map_name[32];
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_range_prop_t *dvma_prop;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs int dvma_prop_len;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t cache_size, tsb_entries;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate mmu state structure and link it to the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * px state structure.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p = kmem_zalloc(sizeof (px_mmu_t), KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (mmu_p == NULL)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (DDI_FAILURE);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_p->px_mmu_p = mmu_p;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_px_p = px_p;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_inst = ddi_get_instance(dip);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Check for "virtual-dma" property that specifies
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the DVMA range.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) !=
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DDI_PROP_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_ATTACH, dip, "Getting virtual-dma failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
b83cd2c35abe58abb09c73f2ef35426f1384ad46Michael Speer kmem_free(mmu_p, sizeof (px_mmu_t));
1c29f7e382074ff2792b7f30c9be898ead487a30Qiyan Sun - Sun Microsystems - San Diego United States px_p->px_mmu_p = NULL;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
8ad8db65d4781f61f1fd519144f555e6045100e1Michael Speer return (DDI_FAILURE);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
fd9489cef0e9b7d8a708339e560d453f230af2cfQiyan Sun - Sun Microsystems - San Diego United States mmu_p->mmu_dvma_base = dvma_prop->dvma_base;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_dvma_end = dvma_prop->dvma_base +
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (dvma_prop->dvma_len - 1);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tsb_entries = MMU_BTOP(dvma_prop->dvma_len);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs kmem_free(dvma_prop, dvma_prop_len);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
a512c5d1f2908d965887ad5494954ba2cf904bd2Qiyan Sun - Sun Microsystems - San Diego United States /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Setup base and bounds for DVMA and bypass mappings.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_dvma_cache_locks =
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs kmem_zalloc(px_dvma_page_cache_entries, KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->dvma_base_pg = MMU_BTOP(mmu_p->mmu_dvma_base);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_dvma_reserve = tsb_entries >> 1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->dvma_end_pg = MMU_BTOP(mmu_p->mmu_dvma_end);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Create a virtual memory map for dvma address space.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reserve 'size' bytes of low dvma space for fast track cache.
b83cd2c35abe58abb09c73f2ef35426f1384ad46Michael Speer */
1c29f7e382074ff2792b7f30c9be898ead487a30Qiyan Sun - Sun Microsystems - San Diego United States (void) snprintf(map_name, sizeof (map_name), "%s%d_dvma",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_driver_name(dip), ddi_get_instance(dip));
8ad8db65d4781f61f1fd519144f555e6045100e1Michael Speer
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cache_size = MMU_PTOB(px_dvma_page_cache_entries *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_page_cache_clustsz);
fd9489cef0e9b7d8a708339e560d453f230af2cfQiyan Sun - Sun Microsystems - San Diego United States mmu_p->mmu_dvma_fast_end = mmu_p->mmu_dvma_base +
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cache_size - 1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_dvma_map = vmem_create(map_name,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void *)(mmu_p->mmu_dvma_fast_end + 1),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MMU_PTOB(tsb_entries) - cache_size, MMU_PAGE_SIZE,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs NULL, NULL, NULL, MMU_PAGE_SIZE, VM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mutex_init(&mmu_p->dvma_debug_lock, NULL, MUTEX_DRIVER, NULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (tsb_i = 0; tsb_i < tsb_entries; tsb_i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs r_addr_t ra = 0;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs io_attributes_t attr;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs caddr_t va;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_getmap(px_p->px_dip, PCI_TSBID(0, tsb_i),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs &attr, &ra) != DDI_SUCCESS)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs continue;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs va = (caddr_t)(MMU_PTOB(mmu_p->dvma_base_pg + tsb_i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (va <= (caddr_t)mmu_p->mmu_dvma_fast_end) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t cache_i;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the va is within the *fast* dvma range; therefore,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * lock its fast dvma page cache cluster in order to
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * both preserve the TTE and prevent the use of this
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fast dvma page cache cluster by px_dvma_map_fast().
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the lock value 0xFF comes from ldstub().
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cache_i = tsb_i / px_dvma_page_cache_clustsz;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ASSERT(cache_i < px_dvma_page_cache_entries);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmu_p->mmu_dvma_cache_locks[cache_i] = 0xFF;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } else {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) vmem_xalloc(mmu_p->mmu_dvma_map, MMU_PAGE_SIZE,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MMU_PAGE_SIZE, 0, 0, va, va + MMU_PAGE_SIZE,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs VM_NOSLEEP | VM_BESTFIT | VM_PANIC);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (DDI_SUCCESS);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs}
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsvoid
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qspx_mmu_detach(px_t *px_p)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs{
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_mmu_t *mmu_p = px_p->px_mmu_p;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) px_lib_iommu_detach(px_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Free the dvma resource map.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs vmem_destroy(mmu_p->mmu_dvma_map);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs kmem_free(mmu_p->mmu_dvma_cache_locks,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_page_cache_entries);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (PX_DVMA_DBG_ON(mmu_p))
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_debug_fini(mmu_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mutex_destroy(&mmu_p->dvma_debug_lock);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Free the mmu state structure.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs kmem_free(mmu_p, sizeof (px_mmu_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_p->px_mmu_p = NULL;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs}
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsint
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qspx_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t npages, size_t pfn_index)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs{
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs dev_info_t *dip = mmu_p->mmu_px_p->px_dip;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs io_attributes_t attr = PX_GET_MP_TTE(mp->dmai_tte);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ASSERT(npages <= mp->dmai_ndvmapages);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages:%x+%x=%x "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "npages=0x%x pfn_index=0x%x\n", (uint_t)mmu_p->dvma_base_pg,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (uint_t)pg_index, dvma_pg, (uint_t)npages, (uint_t)pfn_index);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp, pfn_index,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MMU_MAP_PFN) != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "px_lib_iommu_map failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (DDI_FAILURE);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (!PX_MAP_BUFZONE(mp))
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs goto done;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: redzone pg=%x\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs pg_index + npages);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ASSERT(PX_HAS_REDZONE(mp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index + npages), 1,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs pfn_index + npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: mapping "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "REDZONE page failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_demap(dip, PCI_TSBID(0, pg_index), npages)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_MAP_WIN, dip, "px_lib_iommu_demap: failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (DDI_FAILURE);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsdone:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (PX_DVMA_DBG_ON(mmu_p))
fe930412c257f961ae67039de3b164b83717976aqs px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping,
fe930412c257f961ae67039de3b164b83717976aqs mp->dmai_size, mp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
fe930412c257f961ae67039de3b164b83717976aqs return (DDI_SUCCESS);
fe930412c257f961ae67039de3b164b83717976aqs}
fe930412c257f961ae67039de3b164b83717976aqs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsvoid
fe930412c257f961ae67039de3b164b83717976aqspx_mmu_unmap_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
fe930412c257f961ae67039de3b164b83717976aqs uint_t npages)
fe930412c257f961ae67039de3b164b83717976aqs{
fe930412c257f961ae67039de3b164b83717976aqs px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
fe930412c257f961ae67039de3b164b83717976aqs
fe930412c257f961ae67039de3b164b83717976aqs DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "px_mmu_unmap_pages:%x+%x=%x npages=0x%x\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (uint_t)npages);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs PCI_TSBID(0, pg_index), npages) != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "px_lib_iommu_demap: failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (!PX_MAP_BUFZONE(mp))
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip, "px_mmu_unmap_pages: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "redzone pg=%x\n", pg_index + npages);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ASSERT(PX_HAS_REDZONE(mp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs PCI_TSBID(0, pg_index + npages), 1) != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "px_lib_iommu_demap: failed\n");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs }
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs}
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * px_mmu_map_window - map a dvma window into the mmu
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * used by: px_dma_win(), px_dma_ctlops() - DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * return value: none
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsint
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qspx_mmu_map_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_window_t win_no)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs{
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t obj_pg0_off = mp->dmai_roffset;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t win_pg0_off = win_no ? 0 : obj_pg0_off;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t win_size = mp->dmai_winsize;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t pfn_index = win_size * win_no; /* temp value */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t obj_off = win_no ? pfn_index - obj_pg0_off : 0; /* xferred sz */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t res_size = mp->dmai_object.dmao_size - obj_off + win_pg0_off;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs int ret = DDI_SUCCESS;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ASSERT(!(win_size & MMU_PAGE_OFFSET));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (win_no >= mp->dmai_nwin)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (ret);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (res_size < win_size) /* last window */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs win_size = res_size; /* mp->dmai_winsize unchanged */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mp->dmai_mapping = MMU_PTOB(dvma_pg) | win_pg0_off;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mp->dmai_size = win_size - win_pg0_off; /* cur win xferrable size */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mp->dmai_offset = obj_off; /* win offset into object */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs pfn_index = MMU_BTOP(pfn_index); /* index into pfnlist */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ret = px_mmu_map_pages(mmu_p, mp, dvma_pg, MMU_BTOPR(win_size),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs pfn_index);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (ret);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs}
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * px_mmu_unmap_window
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This routine is called to break down the mmu mappings to a dvma window.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Non partial mappings are viewed as single window mapping.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * used by: px_dma_unbindhdl(), px_dma_window(),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and px_dma_ctlops() - DDI_DMA_FREE, DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * return value: none
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsvoid
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qspx_mmu_unmap_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp)
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer{
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer uint_t npages = MMU_BTOP(mp->dmai_winsize);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer px_mmu_unmap_pages(mmu_p, mp, dvma_pg, npages);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer if (PX_DVMA_DBG_ON(mmu_p))
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer px_dvma_free_debug(mmu_p, (char *)mp->dmai_mapping,
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer mp->dmai_size, mp);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer}
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer#if 0
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer/*
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer * The following table is for reference only. It denotes the
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer * the TSB table size measured in number of 8 byte entries.
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer * It is represented by bits 3:0 in the MMU TSB CTRL REG.
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speerstatic int px_mmu_tsb_sizes[] = {
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x0, /* 1K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x1, /* 2K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x2, /* 4K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x3, /* 8K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x4, /* 16K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x5, /* 32K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x6, /* 64K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x7, /* 128K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer 0x8 /* 256K */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer};
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer#endif
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speerstatic char *px_mmu_errsts[] = {
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer "Protection Error", "Invalid Error", "Timeout", "ECC Error(UE)"
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer};
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer/*ARGSUSED*/
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speerstatic int
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speerpx_log_mmu_err(px_t *px_p)
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer{
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer /*
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer * Place holder, the correct eror bits need tobe logged.
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer */
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer return (0);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer}
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer