audio_4231.h revision 68c47f65208790c466e5e484f2293d3baed71c6a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _AUDIO_4231_H
#define _AUDIO_4231_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Header file for the audiocs device driver.
*/
/*
* Values returned by the AUDIO_GETDEV ioctl()
*/
#define CS_DEV_NAME "SUNW,CS4231"
#define CS_DEV_CONFIG_ONBRD1 "onboard1"
#define CS_DEV_VERSION_A CS_DEV_VERSION
/*
* Driver supported configuration information
*/
#define CS4231_NAME "audiocs"
#define CS4231_MOD_NAME "CS4231 audio driver"
/*
* Implementation specific header file for the audiocs device driver.
*/
#ifdef _KERNEL
enum {
CTL_VOLUME = 0,
};
typedef struct CS_engine CS_engine_t;
typedef struct CS_state CS_state_t;
/*
* These are the registers for the APC DMA channel interface to the
* 4231. One handle provides access the CODEC and the DMA engine's
* registers.
*/
struct cs4231_apc {
};
typedef struct cs4231_apc cs4231_apc_t;
/*
* APC CSR Register bit definitions
*/
#define APC_CLEAR_RESET_VALUE 0x00
#define APC_PLAY_ENABLE (APC_PDMA_GO)
#define APC_PLAY_DISABLE (APC_PDMA_GO)
#define APC_CAP_ENABLE (APC_CDMA_GO)
#define APC_CAP_DISABLE (APC_CDMA_GO)
/*
* These are the registers for the EBUS2 DMA channel interface to the
* 4231. One struct per channel for playback and record, therefore there
* individual handles for the CODEC and the two DMA engines.
*/
struct cs4231_eb2regs {
};
typedef struct cs4231_eb2regs cs4231_eb2regs_t;
/*
* Audio auxio register definitions
*/
/*
* EBUS 2 CSR definitions
*/
/*
* Misc. defines
*/
#define CS4231_REGS (32)
#define CS4231_NCOMPONENTS (1)
#define CS4231_COMPONENT (0)
#define CS4231_PWR_OFF (0)
#define CS4231_PWR_ON (1)
#define CS4231_TIMEOUT (100000)
#define CS4231_PLAY 0
#define CS4231_REC 1
#define CS4231_NFRAMES 4096
#define CS4231_NFRAGS 2
/*
* Supported dma engines and the ops vector
*/
typedef enum cs_dmae_types cs_dmae_types_e;
/*
* Hardware registers
*/
struct cs4231_pioregs {
};
typedef struct cs4231_pioregs cs4231_pioregs_t;
struct cs4231_eb2 {
};
typedef struct cs4231_eb2 cs4231_eb2_t;
struct cs4231_regs {
};
typedef struct cs4231_regs cs4231_regs_t;
/*
* Misc. state enumerations and structures
*/
struct cs4231_handle {
};
typedef struct cs4231_handle cs4231_handle_t;
/*
* CS_port_t - per port (playback or record) state
*/
struct CS_engine {
int ce_num;
unsigned ce_syncdir;
int ce_curidx;
/* registers (EB2 only) */
/* codec enable */
};
struct CS_ctrl {
};
/*
* CS_state_t - per instance state and operation data
*/
struct CS_state {
/*
* Control related fields.
*/
};
/*
* DMA ops vector definition
*/
struct cs4231_dma_ops {
char *dma_device;
int (*cs_dma_map_regs)(CS_state_t *);
void (*cs_dma_unmap_regs)(CS_state_t *);
void (*cs_dma_reset)(CS_state_t *);
int (*cs_dma_start)(CS_engine_t *);
void (*cs_dma_stop)(CS_engine_t *);
void (*cs_dma_power)(CS_state_t *, int);
void (*cs_dma_reload)(CS_engine_t *);
};
typedef struct cs4231_dma_ops cs4231_dma_ops_t;
extern cs4231_dma_ops_t cs4231_apcdma_ops;
extern cs4231_dma_ops_t cs4231_eb2dma_ops;
/*
* Useful bit twiddlers
*/
#define CS4231_RETRIES 10
/*
* CS4231 Register Set Definitions
*/
/* Index Address Register */
/* Status Register */
/* Index 00 - Left ADC Input Control, Modes 1&2 */
/* Index 01 - Right ADC Input Control, Modes 1&2 */
/* Index 02 - Left Aux #1 Input Control, Modes 1&2 */
/* Index 03 - Right Aux #1 Input Control, Modes 1&2 */
/* Index 04 - Left Aux #2 Input Control, Modes 1&2 */
/* Index 05 - Right Aux #2 Input Control, Modes 1&2 */
/* Index 06 - Left DAC Output Control, Modes 1&2 */
/* Index 07 - Right DAC Output Control, Modes 1&2 */
/* Index 08 - Sample Rate and Data Format, Mode 2 only */
#ifdef _BIG_ENDIAN
#define PDF_LINEAR16NE PDF_LINEAR16BE
#else
#define PDF_LINEAR16NE PDF_LINEAR16LE
#endif
/* Index 09 - Interface Configuration, Mode 1&2 */
/* Index 10 - Pin Control, Mode 1&2 */
/* Index 11 - Error Status and Initialization, Mode 1&2 */
/* Index 12 - Mode and ID, Modes 1&2 */
/* Index 13 - Loopback Control, Modes 1&2 */
/* Index 14 - Playback Upper Base, Mode 2 only */
/* Index 15 - Playback Lower Base, Mode 2 only */
/* Index 16 - Alternate Feature Enable 1, Mode 2 only */
/* Index 17 - Alternate Feature Enable 2, Mode 2 only */
/* Index 18 - Left Line Input Control, Mode 2 only */
/* Index 19 - Right Line Input Control, Mode 2 only */
/* Index 20 - Timer Lower Byte, Mode 2 only */
/* Index 21 - Timer Upper Byte, Mode 2 only */
/* Index 22 and 23 are reserved */
/* Index 24 - Alternate Feature Status, Mode 2 only */
/* Index 25 - Version and ID, Mode 2 only */
/* Index 26 - Mono I/O Control, Mode 2 only */
/* Index 27 is reserved */
/* Index 28 - Capture Data Format, Mode 2 only */
#ifdef _BIG_ENDIAN
#define CDF_LINEAR16NE CDF_LINEAR16BE
#else
#define CDF_LINEAR16NE CDF_LINEAR16LE
#endif
/* Index 29 is reserved */
/* Index 30 - Capture Upper Base, Mode 2 only */
/* Index 31 - Capture Lower Base, Mode 2 only */
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _AUDIO_4231_H */