/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
extern "C" {
#endif
/*
* Header file for the audiocs device driver.
*/
/*
* Values returned by the AUDIO_GETDEV ioctl()
*/
/*
* Driver supported configuration information
*/
/*
* Implementation specific header file for the audiocs device driver.
*/
enum {
};
/*
* These are the registers for the APC DMA channel interface to the
* 4231. One handle provides access the CODEC and the DMA engine's
* registers.
*/
};
/*
* APC CSR Register bit definitions
*/
#
define APC_RESET 0x00000001u /* Reset the DMA engine, R/W */#
define APC_CDMA_GO 0x00000004u /* Capture DMA go, R/W */#
define APC_PDMA_GO 0x00000008u /* Playback DMA go, R/W */#
define APC_LOOP_BACK 0x00000010u /* Loopback, Capture to Play */#
define APC_COD_PDWN 0x00000020u /* CODEC power down, R/W */#
define APC_C_ABORT 0x00000040u /* Capture abort, R/W */#
define APC_CXI_EN 0x00000100u /* Capture expired int. enable, R/W */#
define APC_CXI 0x00000200u /* Capture expired interrupt, R/W */#
define APC_CD 0x00000400u /* Capture next VA dirty, R/O */#
define APC_CX 0x00000800u /* Capture expired (pipe empty), R/O */#
define APC_PMI_EN 0x00001000u /* Play pipe empty int. enable, R/W */#
define APC_PD 0x00002000u /* Playback next VA dirty, R/O */#
define APC_PM 0x00004000u /* Play pipe empty, R/O */#
define APC_PMI 0x00008000u /* Play pipe empty interrupt, R/W */#
define APC_EIE 0x00010000u /* Error interrupt enable, R/W */#
define APC_CIE 0x00020000u /* Capture interrupt enable, R/W */#
define APC_PIE 0x00040000u /* Playback interrupt enable, R/W */#
define APC_IE 0x00080000u /* Interrupt enable, R/W */#
define APC_EI 0x00100000u /* Error interrupt, R/W */#
define APC_CI 0x00200000u /* Capture interrupt, R/W */#
define APC_PI 0x00400000u /* Playback interrupt, R/W */#
define APC_IP 0x00800000u /* Interrupt Pending, R/O */#
define APC_ID 0xff000000u /* ID bits, set to 7E, R/O */
/*
* These are the registers for the EBUS2 DMA channel interface to the
* 4231. One struct per channel for playback and record, therefore there
* individual handles for the CODEC and the two DMA engines.
*/
};
/*
* Audio auxio register definitions
*/
/*
* EBUS 2 CSR definitions
*/
#
define EB2_INT_PEND 0x00000001u /* Interrupt pending, R/O */#
define EB2_DRAIN 0x00000004u /* FIFO being drained, R/O */#
define EB2_INT_EN 0x00000010u /* Enable interrupts, R/W */#
define EB2_RESET 0x00000080u /* Reset DMA engine, R/W */#
define EB2_WRITE 0x00000100u /* DMA direction (to mem) R/W */#
define EB2_READ 0x00000000u /* DMA direction (to dev) R/W */#
define EB2_EN_DMA 0x00000200u /* Enable DMA, R/W */#
define EB2_EN_CNT 0x00002000u /* Enable byte count, R/W */#
define EB2_TC 0x00004000u /* Terminal count, R/W */#
define EB2_16 0x00000000u /* 19,18 == 0,0, R/W */#
define EB2_32 0x00040000u /* 19,18 == 0,1, R/W */#
define EB2_4 0x00080000u /* 19,18 == 1,0, R/W */#
define EB2_64 0x000C0000u /* 19,18 == 1,1, R/W */#
define EB2_DIAG_EN 0x00100000u /* DMA diag. enable, R/W */#
define EB2_TCI_DIS 0x00800000u /* Disable TC int., R/W */#
define EB2_EN_NEXT 0x01000000u /* Next addr. enabled, R/W */#
define EB2_DMA_ON 0x02000000u /* DMA engine enabled, R/O */#
define EB2_DEV_ID 0xf0000000u /* Device ID -0x0C, R/O */
/*
* Misc. defines
*/
/*
* Supported dma engines and the ops vector
*/
/*
* Hardware registers
*/
};
};
};
/*
* Misc. state enumerations and structures
*/
};
/*
* CS_port_t - per port (playback or record) state
*/
/* registers (EB2 only) */
/* codec enable */
};
};
/*
* CS_state_t - per instance state and operation data
*/
/*
* Control related fields.
*/
};
/*
* DMA ops vector definition
*/
};
/*
* Useful bit twiddlers
*/
/*
* CS4231 Register Set Definitions
*/
/* Index Address Register */
#
define IAR_TRD 0x20 /* Transfer Request Disable, R/W */#
define IAR_MCE 0x40 /* Mode Change Enable, R/W */#
define IAR_INIT 0x80 /* 4231 init cycle, R/O */
/* Status Register */
#
define STATUS_INT 0x01 /* Interrupt status, R/O */#
define STATUS_SER 0x10 /* Sample Error, see Index 24 */
/* Index 00 - Left ADC Input Control, Modes 1&2 */
#
define LADCI_REG 0x00 /* Left ADC Register */#
define LADCI_LMGE 0x20 /* Left Mic Gain Enable, 20 dB stage */
/* Index 01 - Right ADC Input Control, Modes 1&2 */
#
define RADCI_REG 0x01 /* Right ADC Register */#
define RADCI_RMGE 0x20 /* Right Mic Gain Enable, 20 dB stage */
/* Index 02 - Left Aux #1 Input Control, Modes 1&2 */
#
define LAUX1_REG 0x02 /* Left Aux#1 Register */
/* Index 03 - Right Aux #1 Input Control, Modes 1&2 */
#
define RAUX1_REG 0x03 /* Right Aux#1 Register */
/* Index 04 - Left Aux #2 Input Control, Modes 1&2 */
#
define LAUX2_REG 0x04 /* Left Aux#2 Register */
/* Index 05 - Right Aux #2 Input Control, Modes 1&2 */
#
define RAUX2_REG 0x05 /* Right Aux#2 Register */
/* Index 06 - Left DAC Output Control, Modes 1&2 */
#
define LDACO_REG 0x06 /* Left DAC Register */
/* Index 07 - Right DAC Output Control, Modes 1&2 */
#
define RDACO_REG 0x07 /* Right DAC Register */
/* Index 08 - Sample Rate and Data Format, Mode 2 only */
#
define FSDF_REG 0x08 /* Sample Rate & Data Format Register */#
define FS_5510 0x01 /* XTAL2, Freq. Divide #0 */#
define FS_6620 0x0f /* XTAL2, Freq. Divide #7 */#
define FS_8000 0x00 /* XTAL1, Freq. Divide #0 */#
define FS_9600 0x0e /* XTAL2, Freq. Divide #7 */#
define FS_11025 0x03 /* XTAL2, Freq. Divide #1 */#
define FS_16000 0x02 /* XTAL1, Freq. Divide #1 */#
define FS_18900 0x05 /* XTAL2, Freq. Divide #2 */#
define FS_22050 0x07 /* XTAL2, Freq. Divide #3 */#
define FS_27420 0x04 /* XTAL1, Freq. Divide #2 */#
define FS_32000 0x06 /* XTAL1, Freq. Divide #3 */#
define FS_33075 0x0d /* XTAL2, Freq. Divide #6 */#
define FS_37800 0x09 /* XTAL2, Freq. Divide #4 */#
define FS_44100 0x0b /* XTAL2, Freq. Divide #5 */#
define FS_48000 0x0c /* XTAL1, Freq. Divide #6 */#
define PDF_MONO 0x00 /* Mono Playback */#
define PDF_ULAW8 0x20 /* u-Law, 8-bit companded */#
define PDF_ALAW8 0x60 /* A-Law, 8-bit companded */#
define PDF_ADPCM4 0xa0 /* ADPCM, 4-bit, IMA compatible */#else
#endif
/* Index 09 - Interface Configuration, Mode 1&2 */
#
define INTC_REG 0x09 /* Interrupt Configuration Register */#
define INTC_PEN 0x01 /* Playback enable */#
define INTC_CEN 0x02 /* Capture enable */#
define INTC_SDC 0x04 /* Single DMA channel */#
define INTC_DDC 0x00 /* Dual DMA channels */#
define INTC_ACAL 0x08 /* Auto-Calibrate Enable */
/* Index 10 - Pin Control, Mode 1&2 */
#
define PC_REG 0x0a /* Pin Control Register */#
define PC_IEN 0x02 /* Interrupt Enable */#
define PC_DEN 0x04 /* Dither Enable */#
define PC_XCTL0 0x40 /* External control 0 */#
define PC_XCTL1 0x80 /* External control 1 */
/* Index 11 - Error Status and Initialization, Mode 1&2 */
#
define ESI_REG 0x0b /* Error Status & Init. Register */#
define ESI_DRS 0x10 /* DRQ status */#
define ESI_ACI 0x20 /* Auto-Calibrate In Progress */#
define ESI_PUR 0x40 /* Playback Underrun */#
define ESI_COR 0x80 /* Capture Overrun */
/* Index 12 - Mode and ID, Modes 1&2 */
#
define MID_REG 0x0c /* Mode and ID Register */
/* Index 13 - Loopback Control, Modes 1&2 */
#
define LC_REG 0x0d /* Loopback Control Register */#
define LC_LBE 0x01 /* Loopback Enable */#
define LC_OFF 0x00 /* Loopback off */
/* Index 14 - Playback Upper Base, Mode 2 only */
#
define PUB_REG 0x0e /* Playback Upper Base Register */
/* Index 15 - Playback Lower Base, Mode 2 only */
#
define PLB_REG 0x0f /* Playback Lower Base Register */
/* Index 16 - Alternate Feature Enable 1, Mode 2 only */
#
define AFE1_REG 0x10 /* Alternate Feature Enable 1 Reg */#
define AFE1_TE 0x40 /* Timer Enable */#
define AFE1_OLB 0x80 /* Output Level Bit, 1=2.8Vpp, 0=2Vpp */
/* Index 17 - Alternate Feature Enable 2, Mode 2 only */
#
define AFE2_REG 0x11 /* Alternate Feature Enable 2 Reg */#
define AFE2_HPF 0x01 /* High Pass Filter - DC blocking */
/* Index 18 - Left Line Input Control, Mode 2 only */
#
define LLIC_REG 0x12 /* Left Line Input Control Register */#
define LLIC_LLM 0x80 /* Left Line Mute */
/* Index 19 - Right Line Input Control, Mode 2 only */
#
define RLIC_REG 0x13 /* Right Line Input Control Register */#
define RLIC_RLM 0x80 /* Right Line Mute */
/* Index 20 - Timer Lower Byte, Mode 2 only */
#
define TLB_REG 0x14 /* Timer Lower Byte Register */
/* Index 21 - Timer Upper Byte, Mode 2 only */
#
define TUB_REG 0x15 /* Timer Upper Byte Register */
/* Index 22 and 23 are reserved */
/* Index 24 - Alternate Feature Status, Mode 2 only */
#
define AFS_REG 0x18 /* Alternate Feature Status Register */#
define AFS_PU 0x01 /* Playback Underrun */#
define AFS_PO 0x02 /* Playback Overrun */#
define AFS_CO 0x04 /* Capture Overrun */#
define AFS_CU 0x08 /* Capture Underrun */#
define AFS_PI 0x10 /* Playback Interrupt */#
define AFS_CI 0x20 /* Capture Interrupt */#
define AFS_TI 0x40 /* Timer Interrupt */
/* Index 25 - Version and ID, Mode 2 only */
#
define VID_REG 0x19 /* Version and ID Register */#
define VID_A 0x20 /* Version A */#
define VID_CDE 0x80 /* Versions C, D or E */
/* Index 26 - Mono I/O Control, Mode 2 only */
#
define MIOC_REG 0x1a /* Mono I/O Control Register */#
define MIOC_MOM 0x40 /* Mono Out Mute */#
define MIOC_MIM 0x80 /* Mono In Mute */
/* Index 27 is reserved */
/* Index 28 - Capture Data Format, Mode 2 only */
#
define CDF_REG 0x1c /* Capture Date Foramt Register */#
define CDF_MONO 0x00 /* Mono Capture */#
define CDF_ULAW8 0x20 /* u-Law, 8-bit companded */#
define CDF_ALAW8 0x60 /* A-Law, 8-bit companded */#
define CDF_ADPCM4 0xa0 /* ADPCM, 4-bit, IMA compatible */#else
#endif
/* Index 29 is reserved */
/* Index 30 - Capture Upper Base, Mode 2 only */
#
define CUB_REG 0x1e /* Capture Upper Base Register */
/* Index 31 - Capture Lower Base, Mode 2 only */
#
define CLB_REG 0x1f /* Capture Lower Base Register */
#endif /* _KERNEL */
}
#endif
#endif /* _AUDIO_4231_H */