/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/* Integer Unit simulator for Sparc FPU simulator. */
#include <sys/privregs.h>
#include <sys/vis_simulator.h>
#include <sys/simulate.h>
/*
* Simulator for loads and stores between floating-point unit and memory.
*/
enum ftt_type
void *prw) /* Pointer to locals and ins. */
{
union {
int32_t i;
} fp;
} else {
}
}
return (ftt);
return (ftt);
} else { /* effective address = rs1 + imm13 */
/* Extract simm13 field. */
return (ftt);
}
switch (sz_bits) { /* map size bits to a number */
case 0: /* ldf{a}/stf{a} */
/* Must be word-aligned. */
return (ftt_alignment);
break;
/* Must be word-aligned. */
return (ftt_alignment);
/* Must be extword-aligned. */
return (ftt_alignment);
}
break;
case 2: /* ldqf{a}/stqf{a} */
/* Require only word alignment. */
return (ftt_alignment);
break;
case 3: /* lddf{a}/stdf{a} */
if (get_udatamodel() == DATAMODEL_ILP32) {
/* Require 64 bit-alignment. */
return (ftt_alignment);
} else {
return (ftt_alignment);
}
}
else
case SIMU_FAULT:
return (ftt_fault);
case SIMU_ILLEGAL:
return (ftt_unimplemented);
case SIMU_SUCCESS:
break;
}
return (ftt_none);
}
/*
* Floating-point conditional moves between floating point unit registers.
*/
static enum ftt_type
{
enum icc_type {
} cond;
switch (cc) {
case fcc_0:
break;
case fcc_1:
break;
case fcc_2:
break;
case fcc_3:
break;
default:
return (ftt_unimplemented);
}
switch (cond) {
case fmovn:
moveit = 0;
break;
case fmovl:
break;
case fmovg:
break;
case fmovu:
break;
case fmove:
break;
case fmovlg:
break;
case fmovul:
break;
case fmovug:
break;
case fmovue:
break;
case fmovge:
break;
case fmovle:
break;
case fmovne:
break;
case fmovuge:
break;
case fmovule:
break;
case fmovo:
break;
case fmova:
moveit = 1;
break;
default:
return (ftt_unimplemented);
}
if (moveit) { /* Move fpu register. */
} else { /* fmovd */
/* fix register encoding */
}
}
}
return (ftt_none);
}
/*
* Integer conditional moves between floating point unit registers.
*/
static enum ftt_type
{
int moveit;
enum icc_type {
} cond;
union {
uint32_t i;
} ccr;
switch (cc) {
case icc:
break;
case xcc:
break;
}
switch (cond) {
case fmovn:
moveit = 0;
break;
case fmove:
break;
case fmovle:
break;
case fmovl:
break;
case fmovleu:
break;
case fmovcs:
break;
case fmovneg:
break;
case fmovvs:
break;
case fmova:
moveit = 1;
break;
case fmovne:
break;
case fmovg:
break;
case fmovge:
break;
case fmovgu:
break;
case fmovcc:
break;
case fmovpos:
break;
case fmovvc:
break;
default:
return (ftt_unimplemented);
}
if (moveit) { /* Move fpu register. */
} else { /* fmovd */
/* fix register encoding */
}
}
}
return (ftt_none);
}
/*
* Simulator for moving fp register on condition (FMOVcc).
* FMOVccq (Quad version of instruction) not supported by Ultra-1, so this
* code must always be present.
*/
enum ftt_type
{
} else {
}
}
/*
* Simulator for moving fp register on integer register condition (FMOVr).
* FMOVrq (Quad version of instruction) not supported by Ultra-1, so this
* code must always be present.
*/
enum ftt_type
{
enum rcond_type {
} rcond;
return (ftt_unimplemented);
return (ftt_unimplemented);
return (ftt);
switch (rcond) {
case fmovre:
moveit = r == 0;
break;
case fmovrlez:
moveit = r <= 0;
break;
case fmovrlz:
moveit = r < 0;
break;
case fmovrne:
moveit = r != 0;
break;
case fmovrgz:
moveit = r > 0;
break;
case fmovrgez:
moveit = r >= 0;
break;
default:
return (ftt_unimplemented);
}
if (moveit) { /* Move fpu register. */
} else { /* fmovd */
}
}
}
return (ftt_none);
}
/*
* Move integer register on condition (MOVcc).
*/
enum ftt_type
void *prw, /* Pointer to locals and ins. */
{
enum icc_type {
} cond;
switch (cc) {
case fcc_0:
break;
case fcc_1:
break;
case fcc_2:
break;
case fcc_3:
break;
default:
return (ftt_unimplemented);
}
switch (cond) {
case fmovn:
moveit = 0;
break;
case fmovl:
break;
case fmovg:
break;
case fmovu:
break;
case fmove:
break;
case fmovlg:
break;
case fmovul:
break;
case fmovug:
break;
case fmovue:
break;
case fmovge:
break;
case fmovle:
break;
case fmovne:
break;
case fmovuge:
break;
case fmovule:
break;
case fmovo:
break;
case fmova:
moveit = 1;
break;
default:
return (ftt_unimplemented);
}
if (moveit) { /* Move fpu register. */
uint64_t r;
return (ftt);
} else { /* use sign_ext(simm11) */
union {
int32_t i;
} fp;
}
}
return (ftt);
}