x86_archext.h revision 2ef50f010f7a3a07eb5a9f6001b9843fd868e26b
1N/A * The contents of this file are subject to the terms of the 1N/A * Common Development and Distribution License (the "License"). 1N/A * You may not use this file except in compliance with the License. 1N/A * See the License for the specific language governing permissions 1N/A * and limitations under the License. 1N/A * When distributing Covered Code, include this CDDL HEADER in each 1N/A * If applicable, add the following below this CDDL HEADER, with the 1N/A * fields enclosed by brackets "[]" replaced with your own identifying 1N/A * information: Portions Copyright [yyyy] [name of copyright owner] 1N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 1N/A * Use is subject to license terms. 1N/A * Copyright (c) 2009, Intel Corporation. 1N/A * All rights reserved. 1N/A * cpuid instruction feature flags in %edx (standard function 1) 1N/A /* 0x400 - reserved */ 1N/A /* 0x100000 - reserved */ 1N/A "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
1N/A "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
1N/A "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
1N/A "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1N/A * cpuid instruction feature flags in %ecx (standard function 1) 1N/A /* 0x00000004 - reserved */ 1N/A /* 0x00000800 - reserved */ 1N/A /* 0x00001000 - reserved */ 1N/A /* 0x00008000 - reserved */ 1N/A /* 0x00010000 - reserved */ 1N/A /* 0x00020000 - reserved */ 1N/A "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
1N/A "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
1N/A "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 1N/A * cpuid instruction feature flags in %edx (extended function 0x80000001) 1N/A /* 0x00000400 - sysc on K6m6 */ 1N/A /* 0x00040000 - reserved */ 1N/A /* 0x00080000 - reserved */ 1N/A /* 0x00200000 - reserved */ 1N/A /* 0x10000000 - reserved */ 1N/A "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
1N/A "\30mmx\27mmxext\25nx\22pse\21pat" \
1N/A "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
1N/A "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1N/A "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
1N/A "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 1N/A * Intel now seems to have claimed part of the "extended" function 1N/A * space that we previously for non-Intel implementors to use. 1N/A * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 1N/A * is available in long mode i.e. what AMD indicate using bit 0. 1N/A * On the other hand, everything else is labelled as reserved. 1N/A/* Intel P4 (pre-Prescott, non P4 M) */ 1N/A/* Intel Pentium M */ 1N/A/* Intel P4 (Prescott) */ 1N/A * For Solaris we set up the page attritubute table in the following way: 1N/A * PAT1 Write-Through 1N/A * PAT2 Unchacheable- 1N/A * PAT5 Write-Through 1N/A * PAT6 Write-Combine 1N/A * The only difference from h/w default is entry 6. 1N/A "\40aes\34sse4_2\33sse4_1\32ssse3\31cpuid" \
1N/A "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\
1N/A "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \
1N/A "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 1N/A * flags to patch tsc_read routine. 1N/A * Intel Deep C-State invariant TSC in leaf 0x80000007. 1N/A * Intel Deep C-state always-running local APIC timer 1N/A * x86_type is a legacy concept; this is supplanted 1N/A * for most purposes by x86_feature; modern CPUs 1N/A * should be X86_TYPE_OTHER 1N/A * x86_vendor allows us to select between 1N/A * implementation features and helps guide 1N/A * the interpretation of the cpuid instruction. 1N/A * Vendor string max len + \0 1N/A * a single identifying banner by the vendor. The following encode 1N/A * that "revision" in a uint32_t with the 8 most significant bits 1N/A * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 1N/A * family, and the remaining 16 typically forming a bitmask of revisions 1N/A * within that family with more significant bits indicating "later" revisions. 1N/A/* True if x matches in vendor and family and if x matches the given rev mask */ 1N/A/* True if x matches in vendor and family and rev is at least minx */ * Definitions for AMD Family 0xf. Minor revisions C0 and CG are * sufficiently different that we will distinguish them; in all other * case we will identify the major revision. * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. * Definitions for AMD Family 0x11. * Various socket/package types, extended as the need to distinguish * a new type arises. The top 8 byte identfies the vendor and the * remaining 24 bits describe 24 socket types. * This structure is used to pass arguments and get return values back * from the CPUID instruction in __cpuid_insn() routine. * Defined hardware environments #
define HW_NATIVE 0x00 /* Running on bare metal */#
define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */#
define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */#
define HW_VMWARE 0x03 /* Running on VMware hypervisor */#
endif /* _SYS_X86_ARCHEXT_H */