/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2011 by Delphix. All rights reserved.
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* Copyright 2015 Joyent, Inc.
* Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
* Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
* Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
*/
#ifndef _SYS_X86_ARCHEXT_H
#define _SYS_X86_ARCHEXT_H
#if !defined(_ASM)
#include <sys/processor.h>
#include <vm/seg_enum.h>
#endif /* _ASM */
#ifdef __cplusplus
extern "C" {
#endif
/*
* cpuid instruction feature flags in %edx (standard function 1)
*/
/* 0x400 - reserved */
/* 0x100000 - reserved */
/*
* cpuid instruction feature flags in %ecx (standard function 1)
*/
/* 0x00000004 - reserved */
/* 0x00000800 - reserved */
/* 0x00008000 - reserved */
/* 0x00010000 - reserved */
/* 0x00020000 - reserved */
/*
* cpuid instruction feature flags in %edx (extended function 0x80000001)
*/
/* 0x00000400 - sysc on K6m6 */
/* 0x00040000 - reserved */
/* 0x00080000 - reserved */
/* 0x00200000 - reserved */
/* 0x10000000 - reserved */
/*
* Intel now seems to have claimed part of the "extended" function
* space that we previously for non-Intel implementors to use.
* is available in long mode i.e. what AMD indicate using bit 0.
* On the other hand, everything else is labelled as reserved.
*/
/*
* Intel also uses cpuid leaf 7 to have additional instructions and features.
* Like some other leaves, but unlike the current ones we care about, it
* requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
* with the potential use of additional sub-leaves in the future, we now
* specifically label the EBX features with their leaf and sub-leaf.
*/
#if !defined(__xpv)
/*
* AMD C1E
*/
#endif
/* Intel P6, AMD */
/* Intel P4 (pre-Prescott, non P4 M) */
/* Intel Pentium M */
/* Intel P4 (Prescott) */
#define MTRR_TYPE_UC 0
/*
* For Solaris we set up the page attritubute table in the following way:
* PAT0 Write-Back
* PAT1 Write-Through
* PAT2 Unchacheable-
* PAT3 Uncacheable
* PAT4 Write-Back
* PAT5 Write-Through
* PAT6 Write-Combine
* PAT7 Uncacheable
* The only difference from h/w default is entry 6.
*/
#define PAT_DEFAULT_ATTRIBUTE \
((uint64_t)MTRR_TYPE_WB | \
#define X86FSET_LARGEPAGE 0
/*
* flags to patch tsc_read routine.
*/
/*
* Intel Deep C-State invariant TSC in leaf 0x80000007.
*/
/*
* Intel Deep C-state always-running local APIC timer
*/
/*
* Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
*/
/*
* Intel TSC deadline timer
*/
/*
* x86_type is a legacy concept; this is supplanted
* for most purposes by x86_featureset; modern CPUs
* should be X86_TYPE_OTHER
*/
#define X86_TYPE_OTHER 0
/*
* x86_vendor allows us to select between
* implementation features and helps guide
* the interpretation of the cpuid instruction.
*/
#define X86_VENDOR_Intel 0
/*
* Vendor string max len + \0
*/
/*
* a single identifying banner by the vendor. The following encode
* that "revision" in a uint32_t with the 8 most significant bits
* identifying the vendor with X86_VENDOR_*, the next 8 identifying the
* family, and the remaining 16 typically forming a bitmask of revisions
* within that family with more significant bits indicating "later" revisions.
*/
#define _X86_CHIPREV_VENDOR(x) \
(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
#define _X86_CHIPREV_FAMILY(x) \
(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
#define _X86_CHIPREV_REV(x) \
((x) & _X86_CHIPREV_REV_MASK)
/* True if x matches in vendor and family and if x matches the given rev mask */
/* True if x matches in vendor and family, and rev is at least minx */
/* True if x matches in vendor, and family is at least minx */
/* Revision default */
/*
* Definitions for AMD Family 0xf. Minor revisions C0 and CG are
* sufficiently different that we will distinguish them; in all other
* case we will identify the major revision.
*/
/*
* Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
*/
#define X86_CHIPREV_AMD_10_REV_A \
#define X86_CHIPREV_AMD_10_REV_B \
#define X86_CHIPREV_AMD_10_REV_C2 \
#define X86_CHIPREV_AMD_10_REV_C3 \
#define X86_CHIPREV_AMD_10_REV_D0 \
#define X86_CHIPREV_AMD_10_REV_D1 \
#define X86_CHIPREV_AMD_10_REV_E \
/*
* Definitions for AMD Family 0x11.
*/
#define X86_CHIPREV_AMD_11_REV_B \
/*
* Definitions for AMD Family 0x12.
*/
#define X86_CHIPREV_AMD_12_REV_B \
/*
* Definitions for AMD Family 0x14.
*/
#define X86_CHIPREV_AMD_14_REV_B \
#define X86_CHIPREV_AMD_14_REV_C \
/*
* Definitions for AMD Family 0x15
*/
#define X86_CHIPREV_AMD_15OR_REV_B2 \
#define X86_CHIPREV_AMD_15TN_REV_A1 \
/*
* a new type arises. The top 8 byte identfies the vendor and the
* remaining 24 bits describe 24 socket types.
*/
/*
* AMD socket types
*/
/*
*/
/*
* XFEATURE_ENABLED_MASK values (eax)
*/
#define XFEATURE_FP_ALL \
#if !defined(_ASM)
extern uchar_t x86_featureset[];
extern void free_x86_featureset(void *featureset);
extern void print_x86_featureset(void *featureset);
extern uint_t x86_vendor;
extern uint_t x86_clflush_size;
extern uint_t pentiumpro_bug4046376;
extern const char CyrixInstead[];
#endif
#if defined(_KERNEL)
/*
* This structure is used to pass arguments and get return values back
* from the CPUID instruction in __cpuid_insn() routine.
*/
struct cpuid_regs {
};
/*
*/
extern void invalidate_cache(void);
extern void mtrr_sync(void);
extern void cpu_fast_syscall_enable(void *);
extern void cpu_fast_syscall_disable(void *);
struct cpu;
extern int cpuid_checkpass(struct cpu *, int);
extern const char *cpuid_getvendorstr(struct cpu *);
extern int cpuid_get_chipid(struct cpu *);
extern int cpuid_get_pkgcoreid(struct cpu *);
extern int cpuid_get_clogid(struct cpu *);
extern int cpuid_get_cacheid(struct cpu *);
extern int cpuid_is_cmt(struct cpu *);
extern int cpuid_syscall32_insn(struct cpu *);
extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
extern const char *cpuid_getchiprevstr(struct cpu *);
extern const char *cpuid_getsocketstr(struct cpu *);
extern int cpuid_have_cr8access(struct cpu *);
struct cpuid_info;
extern void setx86isalist(void);
extern void cpuid_alloc_space(struct cpu *);
extern void cpuid_free_space(struct cpu *);
extern void cpuid_pass2(struct cpu *);
extern void cpuid_pass3(struct cpu *);
extern void cpuid_set_cpu_properties(void *, processorid_t,
struct cpuid_info *);
#if !defined(__xpv)
extern void cpuid_mwait_free(struct cpu *);
extern int cpuid_deep_cstates_supported(void);
extern int cpuid_arat_supported(void);
extern int cpuid_iepb_supported(struct cpu *);
extern int cpuid_deadline_tsc_supported(void);
extern void vmware_port(int, uint32_t *);
#endif
struct cpu_ucode_info;
extern void ucode_alloc_space(struct cpu *);
extern void ucode_free_space(struct cpu *);
extern void ucode_check(struct cpu *);
extern void ucode_cleanup();
#if !defined(__xpv)
extern char _tsc_mfence_start;
extern char _tsc_mfence_end;
extern char _tscp_start;
extern char _tscp_end;
extern char _no_rdtsc_start;
extern char _no_rdtsc_end;
extern char _tsc_lfence_start;
extern char _tsc_lfence_end;
#endif
#if !defined(__xpv)
extern char bcopy_patch_start;
extern char bcopy_patch_end;
extern char bcopy_ck_size;
#endif
extern void post_startup_cpu_fixups(void);
#if defined(OPTERON_ERRATUM_93)
extern int opteron_erratum_93;
#endif
#if defined(OPTERON_ERRATUM_91)
extern int opteron_erratum_91;
#endif
#if defined(OPTERON_ERRATUM_100)
extern int opteron_erratum_100;
#endif
#if defined(OPTERON_ERRATUM_121)
extern int opteron_erratum_121;
#endif
#if defined(OPTERON_WORKAROUND_6323525)
extern int opteron_workaround_6323525;
extern void patch_workaround_6323525(void);
#endif
#if !defined(__xpv)
extern void determine_platform(void);
#endif
extern int get_hwenv(void);
extern int is_controldom(void);
extern void xsave_setup_msr(struct cpu *);
/*
* Hypervisor signatures
*/
/*
* Defined hardware environments
*/
#endif /* _KERNEL */
#endif /* !_ASM */
/*
* VMware hypervisor related defines
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_X86_ARCHEXT_H */