/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#include <sys/controlregs.h>
#include <sys/sysevent.h>
#include <sys/pci_cfgspace.h>
#include <sys/mc_intel.h>
#include "nb5000.h"
#include "nb_log.h"
#include "dimm_phys.h"
struct mch_error_code {
};
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_fbd)
if (nerr > 1)
rt = -1;
return (rt);
}
static char *
{
int channel;
if ((ferr_fat_fbd & ERR_FAT_FBD_MASK) == 0) {
return (intr);
}
if ((ferr_fat_fbd & ERR_FAT_FBD_M1) != 0)
else
/*
* If driver was built with closed tree present then we will
* have Intel proprietary code for finding physaddr
*/
if (&dimm_getphys) {
} else {
}
/*
* If there is an offset decoder use it otherwise encode
*/
if (&dimm_getoffset) {
} else {
}
} else {
if ((ferr_fat_fbd & ERR_FAT_FBD_M3) != 0)
else if ((ferr_fat_fbd & ERR_FAT_FBD_M23) != 0) {
intr = "nb.fbd.reset_timeout";
}
}
return (intr);
}
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_fbd)
if (nerr > 1)
rt = -1;
return (rt);
}
static char *
{
if ((ferr_nf_fbd & ERR_NF_FBD_MASK) == 0) {
/* unknown ereport if a recognizable error was not found */
return (intr);
}
if (ferr_nf_fbd & ERR_NF_FBD_MASK) {
if (ferr_nf_fbd & ERR_NF_FBD_ECC_UE) {
/*
* uncorrectable ECC M4 - M12
* we can only isolate to pair of dimms
* for single dimm configuration let eversholt
* sort it out with out needing a special rule
*/
intr = "nb.mem_ue";
} else if (ferr_nf_fbd & ERR_NF_FBD_M13) {
/*
* write error M13
* we can only isolate to pair of dimms
*/
if (nb_mode != NB_MEMORY_MIRROR) {
}
} else if ((ferr_nf_fbd & ERR_NF_FBD_ECC_CE) != 0) {
/* correctable ECC M17-M20 */
if (ecc_locator & 0x1ff)
else if (ecc_locator & 0x3fe00)
intr = "nb.mem_ce";
} else if ((ferr_nf_fbd & ERR_NF_FBD_SPARE) != 0) {
/* spare dimm M27, M28 */
intr = "nb.mem_ds";
}
} else if ((ferr_nf_fbd & ERR_NF_FBD_M22) != 0) {
}
}
/*
* If driver was built with closed tree present then we will
* have Intel proprietary code for finding physaddr
*/
if (&dimm_getphys) {
} else {
}
if (&dimm_getoffset) {
} else {
}
}
return (intr);
}
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_mem)
if (nerr > 1)
rt = -1;
return (rt);
}
static char *
{
int channel;
if ((ferr_nf_mem & ERR_NF_MEM_MASK) == 0) {
/* no first error found */
return (intr);
}
if (ferr_nf_mem & ERR_NF_MEM_MASK) {
if (ferr_nf_mem & ERR_NF_MEM_ECC_UE) {
/*
* uncorrectable ECC M1,M4-M6,M10-M12
* There is only channel per branch
* Invalidate the channel number so the mem ereport
* has the same detector with existing 5000 ereports.
* so we can leverage the existing Everhsolt rule.
*/
if (ferr_nf_mem & ERR_NF_MEM_M1) {
/* check if the nrecmem log is valid */
}
} else {
/* check if the recmem log is valid */
}
}
intr = "nb.ddr2_mem_ue";
} else if ((ferr_nf_mem & ERR_NF_MEM_ECC_CE) != 0) {
/* correctable ECC M14-M16 */
/* check if the recmem log is valid */
}
intr = "nb.ddr2_mem_ce";
} else if ((ferr_nf_mem & ERR_NF_MEM_SPARE) != 0) {
/* spare dimm M20, M21 */
intr = "nb.ddr2_mem_ds";
/*
* The channel can be valid here.
* However, there is only one channel per branch and
* to leverage the eversolt rules of other chipsets,
* the channel is ignored and let the rule find it out
* from the topology.
*/
}
} else if ((ferr_nf_mem & ERR_NF_MEM_M18) != 0) {
}
}
/*
* If driver was built with closed tree present then we will
* have Intel proprietary code for finding physaddr
*/
if (&dimm_getphys) {
} else {
}
if (&dimm_getoffset) {
} else {
}
}
return (intr);
}
};
{ 27, 0, ERR_NF_INT_B27 },
{ 24, 0, ERR_NF_INT_B24 },
{ 18, 0, ERR_NF_INT_B18 },
{ 17, 0, ERR_NF_INT_B17 },
{ 16, 0, ERR_NF_INT_B16 },
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (nb_chipset == INTEL_NB_5400 &&
(err_nf_int & NERR_NF_5400_INT_B26) != 0) {
rt = 26;
nerr++;
}
if (rt)
err_nf_int &= ~ERR_NF_INT_B18;
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_int)
if (nerr > 1)
rt = -1;
return (rt);
}
static int
{
int t = 0;
int rt = 0;
*interpose |= t;
*interpose |= t;
*interpose |= t;
if (!willpanic) {
/*
* if interpose write read-only registers to clear from pcii
* cache
*/
if (*interpose) {
NRECINT_WR();
RECINT_WR();
NRECSF_WR();
RECSF_WR();
}
}
rt = 1;
}
return (rt);
}
static void
{
int t = 0;
*interpose |= t;
*interpose |= t;
*interpose |= t;
if (!willpanic) {
if (*interpose) {
}
}
}
static void
{
}
};
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_fsb)
if (nerr > 1)
rt = -1;
return (rt);
}
static void
{
int t = 0;
*interpose |= t;
*interpose |= t;
*interpose |= t;
if (!willpanic) {
/*
* if interpose write read-only registers to clear from pcii
* cache
*/
if (*interpose) {
}
}
}
{ 0, EMASK_UNCOR_PEX_IO0, PEX_FAT_IO0 }
};
};
{ 0, EMASK_UNCOR_PEX_IO0, PEX_5400_FAT_IO0 }
};
};
};
{ 0, EMASK_UNCOR_PEX_IO0, PEX_NF_IO0 }
};
};
{ 10, 0, PEX_NF_IO10 },
{ 2, 0, PEX_NF_IO2 }
};
};
{ 0, EMASK_UNCOR_PEX_IO0, PEX_5400_NF_IO0 }
};
};
};
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (nerr > 1)
rt = -1;
return (rt);
}
};
};
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (emask_thr)
if (nerr > 1)
rt = -1;
return (rt);
}
static int
{
int nerr = 0;
int i;
int sz;
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
sz = sizeof (fat_unit_pex_5400_error_code) /
sizeof (struct mch_error_code);
for (i = 0; i < sz; i++) {
if (pex_fat &
nerr++;
}
}
sz = sizeof (uncor_pex_5400_error_code) /
sizeof (struct mch_error_code);
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
for (i = 0; i < sz; i++) {
nerr++;
}
}
if (nerr > 1)
rt = -1;
return (rt);
}
static int
{
int t = 0;
*interpose |= t;
*interpose |= t;
*interpose |= t;
return (0);
else
if (!willpanic) {
if (*interpose)
if (*interpose)
if (*interpose)
PEXDEVSTS_WR(pex, 0);
}
return (1);
}
static void
{
int t = 0;
*interpose |= t;
if (!willpanic) {
/*
* if interpose write read-only registers to clear from pcii
* cache
*/
if (*interpose) {
}
}
}
static void
{
int t = 0;
*interpose |= t;
} else {
}
if (!willpanic) {
/*
* if interpose write read-only registers to clear from pcii
* cache
*/
if (*interpose) {
}
}
}
static int
{
int t = 0;
int rt = 0;
/* Memmory err registers */
*interpose |= t;
/* spare rank */
/* RAS registers */
if (!willpanic) {
/*
* if interpose, write read-only registers to clear from pci
* cache
*/
if (*interpose) {
}
}
/*
* In the single channel mode, all dimms are on the channel 0.
* Invalidate this error if the channel number is invalid.
*/
rt = 1;
}
return (rt);
}
static void
{
int interpose = 0;
int spurious = 0;
return;
} else if ((ferr & GE_FBD_FATAL) != 0) {
} else if (nb_chipset == INTEL_NB_5400 &&
}
if (interpose)
else
if (!spurious) {
}
}
static void
{
int interpose = 0;
int spurious = 0;
return;
} else if ((err & GE_NERR_FBD_FATAL) != 0) {
} else if ((err & GE_NERR_FBD_NF) != 0) {
} else if ((err & GE_NERR_MEM_NF) != 0) {
&interpose);
}
if (interpose)
else
if (!spurious) {
}
}
/*ARGSUSED*/
void
{
int nmc = 0;
int i;
if (mutex_tryenter(&nb_mutex) == 0)
return;
nerr = NERR_GLOBAL_RD();
for (i = 0; i < NB_MAX_ERRORS; i++) {
ferr = FERR_GLOBAL_RD();
if (ferr) {
nmc++;
} else if (err) {
nmc++;
}
}
if (nerr) {
}
if (nmc == 0 && nb_mask_mc_set)
}
static void
{
int intel_error_list;
if (intel_error_list >= 0)
else
}
static void
{
int intel_error_list;
if (intel_error_list >= 0)
else
}
static void
{
int intel_error_list;
if (intel_error_list >= 0)
else
}
static void
{
}
}
}
if (sp->intel_error_list >= 0)
else
}
static void
{
}
}
}
}
if (nb_chipset == INTEL_NB_7300) {
NULL);
NULL);
}
NULL);
NULL);
if (nb_chipset == INTEL_NB_7300) {
}
} else {
NULL);
}
if (sp->intel_error_list >= 0)
else
}
static void
{
}
}
}
}
if (sp->intel_error_list >= 0)
else
}
static void
{
}
static void
{
if (data->intel_error_list >= 0) {
} else {
}
}
static void
{
case NB_REG_LOG_FSB:
break;
case NB_REG_LOG_PEX:
break;
case NB_REG_LOG_INT:
break;
case NB_REG_LOG_FAT_FBD:
break;
case NB_REG_LOG_NF_FBD:
break;
case NB_REG_LOG_DMA:
break;
case NB_REG_LOG_THR:
break;
case NB_REG_LOG_NF_MEM:
break;
default:
break;
}
}
void
{
int chip;
if (nb_chipset == INTEL_NB_7300)
else
} else {
}
}
void
{
int hostbridge;
"motherboard", 0);
} else {
"motherboard", 0,
"hostbridge", hostbridge);
}
if (nb_chipset == INTEL_NB_5400) {
} else {
}
} else {
if (nb_chipset == INTEL_NB_5400) {
} else {
}
}
} else {
}
}
void
void *data)
{
"motherboard", 0);
} else {
}
}
void
void *data)
{
char *intr;
"motherboard", 0,
"motherboard", 0,
"motherboard", 0,
} else {
"motherboard", 0);
}
}
void
void *data)
{
char *intr;
"motherboard", 0,
"motherboard", 0,
"motherboard", 0,
} else {
"motherboard", 0);
}
}
void
{
"motherboard", 0);
}
void
void *data)
{
"motherboard", 0);
}
void
void *data)
{
char *intr;
"motherboard", 0,
"motherboard", 0,
"motherboard", 0,
} else {
"motherboard", 0);
}
}
nvlist_t *
{
case NB_REG_LOG_FSB:
break;
case NB_REG_LOG_PEX:
break;
case NB_REG_LOG_INT:
break;
case NB_REG_LOG_FAT_FBD:
break;
case NB_REG_LOG_NF_FBD:
break;
case NB_REG_LOG_DMA:
break;
case NB_REG_LOG_THR:
break;
case NB_REG_LOG_NF_MEM:
break;
default:
"motherboard", 0);
}
return (detector);
}
/*ARGSUSED*/
void
{
if (panicstr) {
return;
/*
* Now try to allocate another element for scratch space and
* use that for further scratch space (eg for constructing
* nvlists to add the main ereport). If we can't reserve
* a scratch element just fallback to working within the
* element we already have, and hope for the best. All this
* is necessary because the fixed buffer nv allocator does
* not reclaim freed space and nvlist construction is
* expensive.
*/
else
} else {
}
return;
/*
* We're done with 'detector' so reclaim the scratch space.
*/
if (panicstr) {
} else {
}
/*
* Encode the error-specific data that was saved in the logout area.
*/
if (panicstr) {
if (scr_eqep)
} else {
}
}