/* BEGIN CSTYLED */
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* Copyright (c) 2009, Intel Corporation.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _I915_DRM_H
#define _I915_DRM_H
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*/
#include "drm.h"
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
typedef struct _drm_i915_init {
enum {
} func;
unsigned int mmio_offset;
int sarea_priv_offset;
unsigned int ring_start;
unsigned int ring_end;
unsigned int ring_size;
unsigned int front_offset;
unsigned int back_offset;
unsigned int depth_offset;
unsigned int w;
unsigned int h;
unsigned int pitch;
unsigned int pitch_bits;
unsigned int back_pitch;
unsigned int depth_pitch;
unsigned int cpp;
unsigned int chipset;
typedef struct _drm_i915_sarea {
int texAge;
int pf_active;
int pad0;
int front_offset;
int front_size;
int back_offset;
int back_size;
int depth_offset;
int depth_size;
int tex_offset;
int tex_size;
int log_tex_granularity;
int pitch;
int rotated_offset;
int rotated_size;
int rotated_pitch;
unsigned int front_tiled;
unsigned int back_tiled;
unsigned int depth_tiled;
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
int pipeA_x;
int pipeA_y;
int pipeA_w;
int pipeA_h;
int pipeB_x;
int pipeB_y;
int pipeB_w;
int pipeB_h;
int pad1;
/* Triple buffering */
int third_offset;
int third_size;
unsigned int third_tiled;
unsigned int front_bo_handle;
unsigned int back_bo_handle;
unsigned int third_bo_handle;
unsigned int depth_bo_handle;
/* Driver specific fence types and classes.
*/
/* The only fence class we support */
#define DRM_I915_FENCE_CLASS_ACCEL 0
/* Fence type that guarantees read-write flush */
/* MI_FLUSH programmed just before the fence */
/* Flags for perf_boxes
*/
/* I915 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
/* Asynchronous page flipping:
*/
typedef struct drm_i915_flip {
/*
* This is really talking about planes, and we could rename it
* except for the fact that some of the duplicated i915_drm.h files
* out there check for HAVE_I915_FLIP and so might pick up this
* version.
*/
int pipes;
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
*/
typedef struct _drm_i915_batchbuffer {
typedef struct _drm_i915_batchbuffer32 {
/* As above, but pass a pointer to userspace buffer which can be
* validated by the kernel prior to sending to hardware.
*/
typedef struct _drm_i915_cmdbuffer {
typedef struct _drm_i915_cmdbuffer32 {
/* Userspace can request & wait on irq's:
*/
typedef struct drm_i915_irq_emit {
typedef struct drm_i915_irq_emit32 {
typedef struct drm_i915_irq_wait {
int irq_seq;
/* Ioctl to query kernel params:
*/
typedef struct drm_i915_getparam {
int param;
typedef struct drm_i915_getparam32 {
int param;
/* Ioctl to set kernel params:
*/
typedef struct drm_i915_setparam {
int param;
int value;
/* A memory manager for regions of shared memory:
*/
typedef struct drm_i915_mem_alloc {
int region;
int alignment;
int size;
typedef struct drm_i915_mem_alloc32 {
int region;
int alignment;
int size;
typedef struct drm_i915_mem_free {
int region;
int region_offset;
typedef struct drm_i915_mem_init_heap {
int region;
int size;
int start;
/* Allow memory manager to be torn down and re-initialized (eg on
* rotate):
*/
typedef struct drm_i915_mem_destroy_heap {
int region;
/* Allow X server to configure which pipes to monitor for vblank signals
*/
typedef struct drm_i915_vblank_pipe {
int pipe;
/* Schedule buffer swap at given vertical blank:
*/
typedef struct drm_i915_vblank_swap {
unsigned int sequence;
#define I915_MMIO_READ 0
#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
typedef struct drm_i915_mmio_entry {
unsigned int flag;
unsigned int offset;
unsigned int size;
typedef struct drm_i915_mmio {
typedef struct drm_i915_hws_addr {
struct drm_i915_gem_init {
/**
* Beginning offset in the GTT to be managed by the DRM memory
* manager.
*/
/**
* Ending offset in the GTT to be managed by the DRM memory
* manager.
*/
};
struct drm_i915_gem_create {
/**
* Requested size for the object.
*
* The (page-aligned) allocated size for the object will be returned.
*/
/**
* Returned handle for the object.
*
* Object handles are nonzero.
*/
};
struct drm_i915_gem_pread {
/** Handle for the object being read. */
/** Offset into the object to read from */
/** Length of data to read */
/**
* Pointer to write the data into.
*
* This is a fixed-size type for 32/64 compatibility.
*/
};
struct drm_i915_gem_pwrite {
/** Handle for the object being written to. */
/** Offset into the object to write to */
/** Length of data to write */
/**
* Pointer to read the data from.
*
* This is a fixed-size type for 32/64 compatibility.
*/
};
struct drm_i915_gem_mmap {
/** Handle for the object being mapped. */
/** Offset in the object to map. */
/**
* Length of data to map.
*
* The value will be page-aligned.
*/
/**
* Returned pointer the data was mapped at.
*
* This is a fixed-size type for 32/64 compatibility.
*/
};
struct drm_i915_gem_mmap_gtt {
/** Handle for the object being mapped. */
/**
* Fake offset to use for subsequent mmap call
*
* This is a fixed-size type for 32/64 compatibility.
*/
};
struct drm_i915_gem_set_domain {
/** Handle for the object */
/** New read domains */
/** New write domain */
};
struct drm_i915_gem_sw_finish {
/** Handle for the object */
};
struct drm_i915_gem_relocation_entry {
/**
* Handle of the buffer being pointed to by this relocation entry.
*
* It's appealing to make this be an index into the mm_validate_entry
* list to refer to the buffer, but this allows the driver to create
* a relocation list for state buffers and not re-write it per
* exec using the buffer.
*/
/**
* Value to be added to the offset of the target buffer to make up
* the relocation entry.
*/
/** Offset in the buffer the relocation entry will be written into */
/**
* Offset value of the target buffer that the relocation entry was last
* written as.
*
* If the buffer has the same offset as last time, we can skip syncing
* and writing the relocation. This value is written back out by
* the execbuffer ioctl when the relocation is written.
*/
/**
* Target memory domains read by this operation.
*/
/**
* Target memory domains written by this operation.
*
* Note that only one domain may be written by the whole
* execbuffer operation, so that where there are conflicts,
* the application will get -EINVAL back.
*/
};
/** @{
* Intel memory domains
*
* Most of these just align with the various caches in
* the system and are used to flush and invalidate as
* objects end up cached in different domains.
*/
/** CPU cache */
/** Render cache, used by 2D and 3D drawing */
/** Sampler cache, used by texture engine */
/** Command queue, used to load batch buffers */
/** Instruction cache, used by shader programs */
/** Vertex address cache */
/** GTT domain - aperture and scanout */
/** @} */
struct drm_i915_gem_exec_object {
/**
* User's handle for a buffer to be bound into the GTT for this
* operation.
*/
/** Number of relocations to be performed on this buffer */
/**
* Pointer to array of struct drm_i915_gem_relocation_entry containing
* the relocations to be performed in this buffer.
*/
/** Required alignment in graphics aperture */
/**
* Returned value of the updated offset of the object, for future
* presumed_offset writes.
*/
};
struct drm_i915_gem_execbuffer {
/**
* List of buffers to be validated with their relocations to be
* performend on them.
*
* This is a pointer to an array of struct drm_i915_gem_validate_entry.
*
* These buffers must be listed in an order such that all relocations
* a buffer is performing refer to buffers that have already appeared
* in the validate list.
*/
/** Offset in the batchbuffer to start execution from. */
/** Bytes used in batchbuffer from batch_start_offset */
/** This is a struct drm_clip_rect *cliprects */
};
struct drm_i915_gem_pin {
/** Handle of the buffer to be pinned. */
/** alignment required within the aperture */
/** Returned GTT offset of the buffer. */
};
struct drm_i915_gem_unpin {
/** Handle of the buffer to be unpinned. */
};
struct drm_i915_gem_busy {
/** Handle of the buffer to check for busy */
/** Return busy status (1 if busy, 0 if idle) */
};
#define I915_TILING_NONE 0
#define I915_BIT_6_SWIZZLE_NONE 0
/* Not seen by userland */
struct drm_i915_gem_set_tiling {
/** Handle of the buffer to have its tiling state updated */
/**
* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
* I915_TILING_Y).
*
* This value is to be set on request, and will be updated by the
* kernel on successful return with the actual chosen tiling layout.
*
* The tiling mode may be demoted to I915_TILING_NONE when the system
* has bit 6 swizzling that can't be managed correctly by GEM.
*
* Buffer contents become undefined when changing tiling_mode.
*/
/**
* Stride in bytes for the object when in I915_TILING_X or
* I915_TILING_Y.
*/
/**
* Returned address bit 6 swizzling required for CPU access through
* mmap mapping.
*/
};
struct drm_i915_gem_get_tiling {
/** Handle of the buffer to get tiling state for. */
/**
* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
* I915_TILING_Y).
*/
/**
* Returned address bit 6 swizzling required for CPU access through
* mmap mapping.
*/
};
struct drm_i915_gem_get_aperture {
/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
/**
* Available space in the aperture used by i915_gem_execbuffer, in
* bytes
*/
};
#endif /* _I915_DRM_H */