/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
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* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Finite State Machines for ATA controller and ATAPI devices
*/
#include "ata_common.h"
#include "atapi.h"
/*
* Local functions
*/
static void
{
ADBG_ERROR(("atapi protocol error: 0x%p 0x%x 0x%x\n",
}
/*
*
* IO CoD DRQ
* -- --- ---
* 0 0 0 == 0 invalid
* 0 0 1 == 1 Data to device
* 0 1 0 == 2 Idle
* 0 1 1 == 3 Send ATAPI CDB to device
* 1 0 0 == 4 invalid
* 1 0 1 == 5 Data from device
* 1 1 0 == 6 Status ready
* 1 1 1 == 7 Future use
*
*/
/*
* Given the current state and the current event this
* table determines what action to take. Note, in the actual
* table I've left room for the invalid event codes: 0, 2, and 7.
*
* +-----------------------------------------------------
* | Current Event
* |
* State | dataout idle cdb datain status
* | 1 2 3 5 6
* |-----------------------------------------------------
* idle | sendcmd sendcmd sendcmd sendcmd sendcmd
* cmd | * * sendcdb * read-err-code
* cdb | xfer-out nada nada xfer-in read-err-code
* datain | * * * xfer-in read-err-code
* dataout | xfer-out * * * read-err-code
* DMA | * * * * read-err-code
*
*/
/* invalid dataout idle cdb invalid datain status future */
};
/*
*
* Give the current state and the current event this table
* determines the new state of the device.
*
* +----------------------------------------------
* | Current Event
* |
* State | dataout idle cdb datain status
* |----------------------------------------------
* idle | cmd cmd cmd cmd cmd
* cmd | * * cdb * *
* cdb | dataout cdb cdb datain (idle)
* datain | * * * datain (idle)
* dataout | dataout * * * (idle)
* DMA | DMA DMA DMA DMA (idle)
*
*
* Note: the states enclosed in parens "(state)", are the accept states
* for this FSM. A separate table is used to encode the done
* states rather than extra state codes.
*
*/
/* invalid dataout idle cdb invalid datain status future */
};
static int
{
/*
* Bug 1256489:
*
* If AC_BSY_WAIT is set, wait for controller to be not busy,
* before issuing a command. If AC_BSY_WAIT is not set,
* skip the wait. This is important for laptops that do
* drop after a resume.
*/
0, ATS_BSY, 5000000)) {
ADBG_WARN(("atapi_start: BSY too long!\n"));
return (ATA_FSM_RC_BUSY);
}
}
/*
* Select the drive
*/
ata_nsecwait(400);
/*
* make certain the drive selected
*/
ADBG_ERROR(("atapi_start_cmd: drive select failed\n"));
return (ATA_FSM_RC_BUSY);
}
/*
* Always make certain interrupts are enabled. It's been reported
* (but not confirmed) that some notebook computers don't
* clear the interrupt disable bit after being resumed. The
* easiest way to fix this is to always clear the disable bit
* before every command.
*/
if (ata_pktp->ap_pciide_dma) {
/*
* DMA but no Overlap
*/
/*
* Physical Region Descriptor Table
*/
} else {
/*
* no DMA and no Overlap
*/
}
/*
* This next one sets the device in motion
*/
/* wait for the busy bit to settle */
ata_nsecwait(400);
/*
* the device will send me an interrupt when it's
* ready for the packet
*/
return (ATA_FSM_RC_OKAY);
}
/* else */
/*
* If we don't receive an interrupt requesting the scsi CDB,
* we must poll for DRQ, and then send out the CDB.
*/
/*
* Wait for DRQ before sending the CDB. Bailout early
* if an error occurs.
*
* I'm not certain what the correct timeout should be.
*/
4000000)) {
/* got good status */
return (ATA_FSM_RC_INTR);
}
ADBG_WARN(("atapi_start_cmd: 0x%x status 0x%x error 0x%x\n",
return (ATA_FSM_RC_INTR);
}
/*
*
* Send the SCSI CDB to the ATAPI device
*
*/
static void
{
int padding;
ADBG_TRACE(("atapi_send_cdb entered\n"));
/*
* send the CDB to the drive
*/
/*
* pad to ad_cdb_len bytes
*/
while (padding) {
padding--;
}
/* wait for the busy bit to settle */
ata_nsecwait(400);
#ifdef ATA_DEBUG_XXX
{
ADBG_TRANSPORT(("\tatapi scsi cmd (%d bytes):\n ",
ata_pktp->ap_cdb_len));
ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n",
ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n",
ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n",
}
#endif
}
/*
* Start the DMA engine
*/
/* ARGSUSED */
static void
{
/*
* Determine the direction. This may look backwards
* but the command bit programmed into the DMA engine
* specifies the type of operation the engine performs
* on the PCI bus (not the ATA bus). Therefore when
* transferring data from the device to system memory, the
* DMA engine performs PCI Write operations.
*/
else
/*
* Start the DMA engine
*/
}
/*
* Transfer the data from the device
*
* Note: the atapi_pio_data_in() and atapi_pio_data_out() functions
* are complicated a lot by the requirement to handle an odd byte count.
* The only device we've seen which does this is the Hitachi CDR-7730.
* See bug ID 1214595. It's my understanding that Dell stopped shipping
* that drive after discovering all the problems it caused, so it may
* be impossible to find one for any sort of regression test.
*
* In the future, ATAPI tape drives will also probably support odd byte
* counts so this code will be excersized more often.
*
*/
static void
{
int drive_bytes;
int xfer_bytes;
int xfer_words;
/*
* Get the device's byte count for this transfer
*/
/*
* Determine actual number I'm going to transfer. My
* buffer might have fewer bytes than what the device
* expects or handles on each interrupt.
*/
ASSERT(xfer_bytes >= 0);
/*
* Round down my transfer count to whole words so that
* if the transfer count is odd it's still handled correctly.
*/
if (xfer_words) {
}
/*
* Handle possible odd byte at end. Read a 16-bit
* word but discard the high-order byte.
*/
if (xfer_bytes & 1) {
drive_bytes -= 2;
}
/*
* Discard any unwanted data.
*/
if (drive_bytes > 0) {
ADBG_TRANSPORT(("atapi_pio_data_in: dump 0x%x bytes\n",
drive_bytes));
/* rounded up if the drive_bytes count is odd */
}
/* wait for the busy bit to settle */
ata_nsecwait(400);
}
/*
* Transfer the data to the device
*/
static void
{
int drive_bytes;
int xfer_bytes;
int xfer_words;
/*
* Get the device's byte count for this transfer
*/
/*
* Determine actual number I'm going to transfer. My
* buffer might have fewer bytes than what the device
* expects or handles on each interrupt.
*/
/*
* Round down my transfer count to whole words so that
* if the transfer count is odd it's handled correctly.
*/
if (xfer_words) {
}
/*
* If odd byte count, transfer the last
* byte. Use a tmp so that I don't run off
* the end off the buffer and possibly page
* fault.
*/
if (xfer_bytes & 1) {
/* grab the last unsigned byte and widen it to 16-bits */
}
/* wait for the busy bit to settle */
ata_nsecwait(400);
}
/*
*
* check status of completed command
*
*/
static void
int dma_completion)
{
}
}
/*
* If the DMA transfer failed leave the resid set to
* the original byte count. The target driver has
* to do a REQUEST SENSE to get the true residual
* byte count. Otherwise, it all transferred so update
* the flags and residual byte count.
*/
}
}
static void
{
/* select the drive */
ata_nsecwait(400);
/* issue atapi DEVICE RESET */
/* wait for the busy bit to settle */
ata_nsecwait(400);
/*
* Re-select the drive (this is probably only necessary
* when resetting drive 1).
*/
ata_nsecwait(400);
/* allow the drive the full 6 seconds to respond */
/* LINTED */
ADBG_WARN(("atapi_device_reset: still busy\n"));
/*
* It's not clear to me what to do at this point,
* the drive might be dead or might eventually
* recover. For now just ignore it and continue
* to attempt to use the drive.
*/
}
}
void
{
int drive;
/*
* reset drive drive 0 and the drive 1
*/
}
}
}
int
{
int rc;
ADBG_TRACE(("atapi_start entered\n"));
/*
* check for valid state
*/
ADBG_ERROR(("atapi_fsm_start not idle 0x%x\n",
return (ATA_FSM_RC_BUSY);
} else {
}
switch (rc) {
case ATA_FSM_RC_OKAY:
/*
* The command started okay. Just return.
*/
break;
case ATA_FSM_RC_INTR:
/*
* Got Command Phase. The upper layer will send
* the cdb by faking an interrupt.
*/
break;
case ATA_FSM_RC_FINI:
/*
* command completed immediately, stick on done q
*/
break;
case ATA_FSM_RC_BUSY:
/*
* The command wouldn't start, tell the upper layer to
* stick this request on the done queue.
*/
return (ATA_FSM_RC_BUSY);
}
return (rc);
}
/*
*
* All interrupts on an ATAPI device come through here.
* This function determines what to do next, based on
* the current state of the request and the drive's current
* status bits. See the FSM tables at the top of this file.
*
*/
int
{
/*
* get the prior state
*/
/*
* If doing DMA, then:
*
* 1. halt the DMA engine
* 2. reset the interrupt and error latches
* 3. reset the drive's IRQ.
*
* I think the order of these operations must be
* exactly as listed. Otherwise we the PCI-IDE
* controller can hang or we can miss the next interrupt
* edge.
*
*/
switch (state) {
case S_DMA:
/*
* Halt the DMA engine. When we reach this point
* we already know for certain that the device has
* an interrupt pending since the ata_get_status()
* function already checked the PCI-IDE interrupt
* status bit.
*/
/*FALLTHRU*/
case S_IDLE:
case S_CMD:
case S_CDB:
case S_IN:
case S_OUT:
break;
}
/*
* Clear the PCI-IDE latches and the drive's IRQ
*/
/*
* some non-compliant (i.e., NEC) drives don't
* it asserted until they're actually non-busy.
* There's a small window between reading the alt_status
* and status registers where the drive might "bounce"
* the ATS_BSY bit.
*/
return (ATA_FSM_RC_BUSY);
/*
* get the interrupt reason code
*/
/*
* encode the status and interrupt reason bits
* into an event code which is used to index the
* FSM tables
*/
/*
* determine the action for this event
*/
/*
* determine the new state
*/
switch (action) {
default:
case A_UNK:
/*
* invalid state
*/
/*
* ??? this shouldn't happen. ???
* if there's an active command on
* this device, the pkt timer should eventually clear the
* device. I might try sending a DEVICE-RESET here to speed
* up the error recovery except that DEVICE-RESET is kind of
* complicated to implement correctly because if I send a
* DEVICE-RESET to drive 1 it deselects itself.
*/
ADBG_WARN(("atapi_fsm_intr: Unsupported intr\n"));
break;
case A_NADA:
drv_usecwait(100);
break;
case A_CDB:
/*
* send out atapi pkt
*/
/*
* start the DMA engine if necessary and change
* the state variable to reflect not doing PIO
*/
if (ata_pktp->ap_pciide_dma) {
}
break;
case A_IN:
/*
* maybe this was a spurious interrupt, just
* spin for a bit and see if the drive
* recovers
*/
drv_usecwait(100);
break;
}
/*
* read in the data
*/
if (!ata_pktp->ap_pciide_dma) {
}
break;
case A_OUT:
/* spin for a bit and see if the drive recovers */
drv_usecwait(100);
break;
}
/*
* send out data
*/
if (!ata_pktp->ap_pciide_dma) {
}
break;
case A_IDLE:
/*
* The DRQ bit deasserted before or between the data
* transfer phases.
*/
if (!ata_drvp->ad_bogus_drq) {
}
drv_usecwait(100);
break;
case A_RE:
/*
* If we get here, a command has completed!
*
* check status of completed command
*/
return (ATA_FSM_RC_FINI);
case A_REX:
/*
* some NEC drives don't report the right interrupt
* reason code for the status phase
*/
if (!ata_drvp->ad_nec_bad_status) {
drv_usecwait(100);
}
return (ATA_FSM_RC_FINI);
}
return (ATA_FSM_RC_OKAY);
}