/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#ifndef _SYS_PCI_CFGSPACE_IMPL_H
#define _SYS_PCI_CFGSPACE_IMPL_H
/*
* Routines to support particular PCI chipsets
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* Generic Mechanism 1 routines
* XX64 putb -> put8, putw -> put16 etc.
*/
/*
* AMD family >= 0x10 Mechanism 1 routines with ECS support
*/
extern boolean_t pci_check_amd_ioecs(void);
/*
* Generic Mechanism 2 routines
*/
/*
* Intel Neptune routines. Neptune is Mech 1, except that BIOSes
* often initialize it into Mech 2 so we dynamically switch it to
* Mech 1. The chipset's buggy, so we have to do it carefully.
*/
extern boolean_t pci_check_neptune(void);
/*
* Intel Orion routines. Orion is Mech 1, except that there's a bug
* in the peer bridge that requires that it be tweaked specially
* around accesses to config space.
*/
extern boolean_t pci_is_broken_orion(void);
/*
* Generic PCI constants. Probably these should be in pci.h.
*/
/*
* PCI access mechanism constants. Probably these should be in pci_impl.h.
*/
extern uint64_t mcfg_mem_base;
extern uint8_t mcfg_bus_start;
extern uint8_t mcfg_bus_end;
/*
* Mutexes for pci config space routines
*/
extern kmutex_t pcicfg_mutex;
extern kmutex_t pcicfg_mmio_mutex;
/*
*/
extern kmutex_t pcicfg_chipset_mutex;
/*
* pci get irq routing information support
*/
/*
* low-mem addresses for irq routing bios operations
* We set up the initial request for up to 32 table entries, and will
* re-issue for up to 255 entries if the bios indicates it requires
* a larger table. 255 entries plus the header would consume the
* memory between 0x7000-0x7fff.
*/
#pragma pack(1)
typedef struct pci_irq_route {
#pragma pack()
#pragma pack(1)
typedef struct pci_irq_route_hdr {
#pragma pack()
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_CFGSPACE_IMPL_H */