/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* ================================================================
* Multiprocessor AMD and Intel systems may have Non Uniform Memory Access
* (NUMA). A NUMA machine consists of one or more "nodes" that each consist of
* one or more CPUs and some local memory. The CPUs in each node can access
* the memory in the other nodes but at a higher latency than accessing their
* local memory. Typically, a system with only one node has Uniform Memory
* Access (UMA), but it may be possible to have a one node system that has
* some global memory outside of the node which is higher latency.
*
* Module Description
* ------------------
* This module provides a platform interface for determining which CPUs and
* which memory (and how much) are in a NUMA node and how far each node is from
* each other. The interface is used by the Virtual Memory (VM) system and the
* common lgroup framework. The VM system uses the plat_*() routines to fill
* in its memory node (memnode) array with the physical address range spanned
* by each NUMA node to know which memory belongs to which node, so it can
* build and manage a physical page free list for each NUMA node and allocate
* local memory from each node as needed. The common lgroup framework uses the
* exported lgrp_plat_*() routines to figure out which CPUs and memory belong
* to each node (leaf lgroup) and how far each node is from each other, so it
* can build the latency (lgroup) topology for the machine in order to optimize
* for locality. Also, an lgroup platform handle instead of lgroups are used
* in the interface with this module, so this module shouldn't need to know
* anything about lgroups. Instead, it just needs to know which CPUs, memory,
* etc. are in each NUMA node, how far each node is from each other, and to use
* a unique lgroup platform handle to refer to each node through the interface.
*
* Determining NUMA Configuration
* ------------------------------
* By default, this module will try to determine the NUMA configuration of the
* machine by reading the ACPI System Resource Affinity Table (SRAT) and System
* Locality Information Table (SLIT). The SRAT contains info to tell which
* CPUs and memory are local to a given proximity domain (NUMA node). The SLIT
* is a matrix that gives the distance between each system locality (which is
* a NUMA node and should correspond to proximity domains in the SRAT). For
* more details on the SRAT and SLIT, please refer to an ACPI 3.0 or newer
* specification.
*
* If the SRAT doesn't exist on a system with AMD Opteron processors, we
* examine registers in PCI configuration space to determine how many nodes are
* in the system and which CPUs and memory are in each node.
* do while booting the kernel.
*
* NOTE: Using these PCI configuration space registers to determine this
* locality info is not guaranteed to work or be compatible across all
* Opteron processor families.
*
* If the SLIT does not exist or look right, the kernel will probe to determine
* the distance between nodes as long as the NUMA CPU and memory configuration
* has been determined (see lgrp_plat_probe() for details).
*
* Data Structures
* ---------------
* The main data structures used by this code are the following:
*
* - lgrp_plat_cpu_node[] CPU to node ID mapping table indexed by
* CPU ID (only used for SRAT)
*
* - lgrp_plat_lat_stats.latencies[][] Table of latencies between same and
* different nodes indexed by node ID
*
* - lgrp_plat_node_cnt Number of NUMA nodes in system for
* non-DR-capable systems,
* maximum possible number of NUMA nodes
* in system for DR capable systems.
*
* - lgrp_plat_node_domain[] Node ID to proximity domain ID mapping
* table indexed by node ID (only used
* for SRAT)
*
* - lgrp_plat_memnode_info[] Table with physical address range for
* each memory node indexed by memory node
* ID
*
* The code is implemented to make the following always be true:
*
* lgroup platform handle == node ID == memnode ID
*
* Moreover, it allows for the proximity domain ID to be equal to all of the
* above as long as the proximity domains IDs are numbered from 0 to <number of
* nodes - 1>. This is done by hashing each proximity domain ID into the range
* from 0 to <number of nodes - 1>. Then proximity ID N will hash into node ID
* N and proximity domain ID N will be entered into lgrp_plat_node_domain[N]
* and be assigned node ID N. If the proximity domain IDs aren't numbered
* from 0 to <number of nodes - 1>, then hashing the proximity domain IDs into
* lgrp_plat_node_domain[] will still work for assigning proximity domain IDs
* to node IDs. However, the proximity domain IDs may not map to the
* equivalent node ID since we want to keep the node IDs numbered from 0 to
* <number of nodes - 1> to minimize cost of searching and potentially space.
*
* With the introduction of support of memory DR operations on x86 platforms,
* things get a little complicated. The addresses of hot-added memory may not
* be continuous with other memory connected to the same lgrp node. In other
* words, memory addresses may get interleaved among lgrp nodes after memory
* DR operations. To work around this limitation, we have extended the
* relationship between lgrp node and memory node from 1:1 map to 1:N map,
* that means there may be multiple memory nodes associated with a lgrp node
* after memory DR operations.
*
* To minimize the code changes to support memory DR operations, the
* following policies have been adopted.
* 1) On non-DR-capable systems, the relationship among lgroup platform handle,
* node ID and memnode ID is still kept as:
* lgroup platform handle == node ID == memnode ID
* 2) For memory present at boot time on DR capable platforms, the relationship
* is still kept as is.
* lgroup platform handle == node ID == memnode ID
* 3) For hot-added memory, the relationship between lgrp ID and memnode ID have
* been changed from 1:1 map to 1:N map. Memnode IDs [0 - lgrp_plat_node_cnt)
* are reserved for memory present at boot time, and memnode IDs
* [lgrp_plat_node_cnt, max_mem_nodes) are used to dynamically allocate
* memnode ID for hot-added memory.
* 4) All boot code having the assumption "node ID == memnode ID" can live as
* is, that's because node ID is always equal to memnode ID at boot time.
* 5) The lgrp_plat_memnode_info_update(), plat_pfn_to_mem_node() and
* lgrp_plat_mem_size() related logics have been enhanced to deal with
* the 1:N map relationship.
* 6) The latency probing related logics, which have the assumption
* "node ID == memnode ID" and may be called at run time, is disabled if
* memory DR operation is enabled.
*/
#include <sys/bootconf.h>
#include <sys/controlregs.h>
#include <sys/machsystm.h>
#include <sys/pci_cfgspace.h>
#include <sys/pci_impl.h>
#include <sys/sysmacros.h>
#include <sys/x86_archext.h>
#include <vm/seg_kmem.h>
/* from fakebop.c */
extern ACPI_TABLE_SRAT *srat_ptr;
extern ACPI_TABLE_SLIT *slit_ptr;
extern ACPI_TABLE_MSCT *msct_ptr;
/*
* Constants for configuring probing
*/
/*
* Flags for probing
*/
/*
* Hash proximity domain ID into node to domain mapping table "mod" number of
* nodes to minimize span of entries used and try to have lowest numbered
* proximity domain be node 0
*/
/*
* CPU to node ID mapping structure (only used with SRAT)
*/
typedef struct cpu_node_map {
int exists;
/*
* Latency statistics
*/
typedef struct lgrp_plat_latency_stats {
/*
* Memory configuration for probing
*/
typedef struct lgrp_plat_probe_mem_config {
/*
* Statistics kept for probing
*/
typedef struct lgrp_plat_probe_stats {
/*
* Node to proximity domain ID mapping structure (only used with SRAT)
*/
typedef struct node_domain_map {
int exists;
/*
* Node ID and starting and ending page for physical memory in memory node
*/
typedef struct memnode_phys_addr_map {
int exists;
/*
* Number of CPUs for which we got APIC IDs
*/
static int lgrp_plat_apic_ncpus = 0;
/*
* CPU to node ID mapping table (only used for SRAT) and its max number of
* entries
*/
/*
* Latency statistics
*/
/*
* Whether memory is interleaved across nodes causing MPO to be disabled
*/
static int lgrp_plat_mem_intrlv = 0;
/*
* Node ID to proximity domain ID mapping table (only used for SRAT)
*/
/*
* Physical address range for memory in each node
*/
/*
* Statistics gotten from probing
*/
/*
* Memory configuration for probing
*/
/*
* Lowest proximity domain ID seen in ACPI SRAT
*/
/*
* Error code from processing ACPI SRAT
*/
static int lgrp_plat_srat_error = 0;
/*
* Error code from processing ACPI SLIT
*/
static int lgrp_plat_slit_error = 0;
/*
* Whether lgrp topology has been flattened to 2 levels.
*/
static int lgrp_plat_topo_flatten = 0;
/*
* Maximum memory node ID in use.
*/
/*
* Allocate lgroup array statically
*/
static int nlgrps_alloc;
/*
* Enable finding and using minimum proximity domain ID when hashing
*/
/*
* Maximum possible number of nodes in system
*/
/*
* Enable sorting nodes in ascending order by starting physical address
*/
/*
* Configuration Parameters for Probing
* - lgrp_plat_probe_flags Flags to specify enabling probing, probe
* operation, etc.
* - lgrp_plat_probe_nrounds How many rounds of probing to do
* - lgrp_plat_probe_nsamples Number of samples to take when probing each
* node
* - lgrp_plat_probe_nreads Number of times to read vendor ID from
* Northbridge for each probe
*/
/*
* Enable use of ACPI System Resource Affinity Table (SRAT), System
* Locality Information Table (SLIT) and Maximum System Capability Table (MSCT)
*/
/*
* mnode_xwa: set to non-zero value to initiate workaround if large pages are
* found to be crossing memory node boundaries. The workaround will eliminate
* a base size page at the end of each memory node boundary to ensure that
* a large page with constituent pages that span more than 1 memory node
* can never be formed.
*
*/
/*
* Static array to hold lgroup statistics
*/
/*
* Forward declarations of platform interface routines
*/
/*
* Forward declarations of lgroup platform interface routines
*/
int lgrp_plat_max_lgrps(void);
void lgrp_plat_probe(void);
lgrp_handle_t lgrp_plat_root_hand(void);
/*
* Forward declarations of local routines
*/
static int is_opteron(void);
int cpu_node_nentries);
static void lgrp_plat_get_numa_config(void);
static void lgrp_plat_main_init(void);
static void lgrp_plat_release_bootstrap(void);
/*
* PLATFORM INTERFACE ROUTINES
*/
/*
* Configure memory nodes for machines with more than one node (ie NUMA)
*/
void
{
/*
* Boot install lists are arranged <addr, len>, ...
*/
while (list) {
int node;
continue;
}
/*
* When there is only one memnode, just add memory to memnode
*/
if (max_mem_nodes == 1) {
continue;
}
/*
* mem_node_add_slice() expects to get a memory range that
* is within one memnode, so need to split any memory range
* that spans multiple memnodes into subranges that are each
* contained within one memnode when feeding them to
* mem_node_add_slice()
*/
do {
/*
* Panic if DRAM address map registers or SRAT say
* memory in node doesn't exist or address from
* boot installed memory list entry isn't in this node.
* This shouldn't happen and rest of code can't deal
* with this if it does.
*/
"to add installed memory address 0x%lx\n",
}
/*
* End of current subrange should not span memnodes
*/
endcnt = 0;
if (mnode_xwa > 1) {
/*
* sacrifice the last page in each
* node to eliminate large pages
* that span more than 1 memory node.
*/
endcnt = 1;
}
}
/*
* Next subrange starts after end of current one
*/
}
mem_node_physalign = 0;
mem_node_pfn_shift = 0;
}
/*
* plat_mnode_xcheck: checks the node memory ranges to see if there is a pfncnt
* range of pages aligned on pfncnt that crosses an node boundary. Returns 1 if
* a crossing is found and returns 0 otherwise.
*/
int
{
continue;
if (prevnode == -1) {
continue;
}
/* assume x86 node pfn ranges are in increasing order */
/*
* continue if the starting address of node is not contiguous
* with the previous node.
*/
continue;
}
/* check if the starting address of node is pfncnt aligned */
/*
* at this point, node starts at an unaligned boundary
* and is contiguous with the previous node(s) to
* basenode. Check if there is an aligned contiguous
* range of length pfncnt that crosses this boundary.
*/
pfncnt);
pfncnt);
/*
* large page found to cross mnode boundary.
* Return Failure if workaround not enabled.
*/
if (mnode_xwa == 0)
return (1);
mnode_xwa++;
}
}
}
return (0);
}
{
if (max_mem_nodes == 1)
return (LGRP_DEFAULT_HANDLE);
}
int
{
int node;
if (max_mem_nodes == 1)
return (0);
/*
* Skip nodes with no memory
*/
continue;
return (node);
}
/*
* Didn't find memnode where this PFN lives which should never happen
*/
return (-1);
}
/*
* LGROUP PLATFORM INTERFACE ROUTINES
*/
/*
* Allocate additional space for an lgroup.
*/
lgrp_t *
{
return (NULL);
return (lgrp);
}
/*
* Platform handling for (re)configuration changes
*
* Mechanism to protect lgrp_plat_cpu_node[] at CPU hotplug:
* 1) Use cpu_lock to synchronize between lgrp_plat_config() and
* lgrp_plat_cpu_to_hand().
* 2) Disable latency probing logic by making sure that the flag
* LGRP_PLAT_PROBE_ENABLE is cleared.
*
* Mechanism to protect lgrp_plat_memnode_info[] at memory hotplug:
* 1) Only inserts into lgrp_plat_memnode_info at memory hotplug, no removal.
* 2) Only expansion to existing entries, no shrinking.
* 3) On writing side, DR framework ensures that lgrp_plat_config() is called
* in single-threaded context. And membar_producer() is used to ensure that
* all changes are visible to other CPUs before setting the "exists" flag.
* 4) On reading side, membar_consumer() after checking the "exists" flag
* ensures that right values are retrieved.
*
* Mechanism to protect lgrp_plat_node_domain[] at hotplug:
* 1) Only insertion into lgrp_plat_node_domain at hotplug, no removal.
* 2) On writing side, it's single-threaded and membar_producer() is used to
* ensure all changes are visible to other CPUs before setting the "exists"
* flag.
* 3) On reading side, membar_consumer() after checking the "exists" flag
* ensures that right values are retrieved.
*/
void
{
#ifdef __xpv
#else
extern void acpidev_dr_free_cpu_numa_info(void *);
/*
* Don't bother here if it's still during boot or only one lgrp node
* is supported.
*/
return;
switch (flag) {
case LGRP_CONFIG_CPU_ADD:
/* Check whether CPU already exists. */
"!lgrp: CPU(%d) already exists in cpu_node map.",
break;
}
/* Query CPU lgrp information. */
if (rc != 0) {
"!lgrp: failed to query lgrp info for CPU(%d).",
break;
}
/* Update node to proximity domain mapping */
if (node == -1) {
if (node == -1) {
"node_domain map for domain(%u).", domain);
break;
}
}
/* Update latency information among lgrps. */
&lgrp_plat_lat_stats) != 0) {
"latency information for domain (%u).",
domain);
}
}
/* Update CPU to node mapping. */
break;
case LGRP_CONFIG_CPU_DEL:
/* Check whether CPU exists. */
"!lgrp: CPU(%d) doesn't exist in cpu_node map.",
break;
}
/* Query CPU lgrp information. */
if (rc != 0) {
"!lgrp: failed to query lgrp info for CPU(%d).",
break;
}
/* Update map. */
break;
case LGRP_CONFIG_MEM_ADD:
/* Update latency information among lgrps. */
&lgrp_plat_lat_stats) != 0) {
"latency information for domain (%u).",
domain);
}
}
"!lgrp: failed to update latency information for "
}
break;
default:
break;
}
#endif /* __xpv */
}
/*
* Return the platform handle for the lgroup containing the given CPU
*/
{
if (lgrp_plat_node_cnt == 1)
return (LGRP_DEFAULT_HANDLE);
return (LGRP_NULL_HANDLE);
return (hand);
}
/*
* Platform-specific initialization of lgroups
*/
void
{
#if defined(__xpv)
#else /* __xpv */
#endif /* __xpv */
switch (stage) {
case LGRP_INIT_STAGE1:
#if defined(__xpv)
/*
* XXPV For now, the hypervisor treats all memory equally.
*/
#else /* __xpv */
/*
* Get boot property for lgroup topology height limit
*/
(void) lgrp_topo_ht_limit_set((int)value);
/*
*/
lgrp_plat_srat_enable = (int)value;
/*
*/
lgrp_plat_slit_enable = (int)value;
/*
*/
lgrp_plat_msct_enable = (int)value;
/*
* Initialize as a UMA machine
*/
if (lgrp_topo_ht_limit() == 1) {
return;
}
/*
* Each lgrp node needs MAX_MEM_NODES_PER_LGROUP memnodes
* to support memory DR operations if memory DR is enabled.
*/
}
#endif /* __xpv */
break;
case LGRP_INIT_STAGE3:
break;
case LGRP_INIT_STAGE4:
break;
default:
break;
}
}
/*
* Return latency between "from" and "to" lgroups
*
* This latency number can only be used for relative comparison
* between lgroups on the running system, cannot be used across platforms,
* and may not reflect the actual latency. It is platform and implementation
* specific, so platform gets to decide its value. It would be nice if the
* number was at least proportional to make comparisons more meaningful though.
*/
int
{
int node;
if (max_mem_nodes == 1)
return (0);
/*
* Return max latency for root lgroup
*/
return (lgrp_plat_lat_stats.latency_max);
/*
* Return 0 for nodes (lgroup platform handles) out of range
*/
return (0);
/*
* Probe from current CPU if its lgroup latencies haven't been set yet
* and we are trying to get latency from current CPU to some node.
*/
/*
* Latency information should be updated by lgrp_plat_config()
* for DR operations. Something is wrong if reaches here.
* For safety, flatten lgrp topology to two levels.
*/
if (plat_dr_support_cpu() || plat_dr_support_memory()) {
"lgrp: failed to get latency information, "
"fall back to two-level topology.");
} else {
}
}
}
/*
* Return the maximum number of lgrps supported by the platform.
* Before lgrp topology is known it returns an estimate based on the number of
* nodes. Once topology is known it returns:
* are not suppported.
* supported.
*/
int
lgrp_plat_max_lgrps(void)
{
if (!lgrp_topo_initialized || plat_dr_support_cpu() ||
} else {
return (lgrp_alloc_max + 1);
}
}
/*
* Count number of memory pages (_t) based on mnode id (_n) and query type (_t).
*/
switch (_q) { \
case LGRP_MEM_SIZE_FREE: \
break; \
case LGRP_MEM_SIZE_AVAIL: \
break; \
case LGRP_MEM_SIZE_INSTALL: \
break; \
default: \
break; \
} \
}
/*
* Return the number of free pages in an lgroup.
*
* For query of LGRP_MEM_SIZE_FREE, return the number of base pagesize
* pages on freelists. For query of LGRP_MEM_SIZE_AVAIL, return the
* number of allocatable base pagesize pages corresponding to the
* lgroup (e.g. do not include page_t's, BOP_ALLOC()'ed memory, ..)
* For query of LGRP_MEM_SIZE_INSTALL, return the amount of physical
* memory installed, regardless of whether or not it's usable.
*/
{
int mnode;
extern struct memlist *phys_avail;
extern struct memlist *phys_install;
if (plathand == LGRP_DEFAULT_HANDLE)
if (plathand != LGRP_NULL_HANDLE) {
/* Count memory node present at boot. */
/* Count possible hot-added memory nodes. */
for (mnode = lgrp_plat_node_cnt;
}
}
return (npgs);
}
/*
* Return the platform handle of the lgroup that contains the physical memory
* corresponding to the given page frame number
*/
{
int mnode;
if (max_mem_nodes == 1)
return (LGRP_DEFAULT_HANDLE);
return (LGRP_NULL_HANDLE);
if (mnode < 0)
return (LGRP_NULL_HANDLE);
return (MEM_NODE_2_LGRPHAND(mnode));
}
/*
* Probe memory in each node from current CPU to determine latency topology
*
* The probing code will probe the vendor ID register on the Northbridge of
* Opteron processors and probe memory for other processors by default.
*
* Since probing is inherently error prone, the code takes laps across all the
* nodes probing from each node to each of the other nodes some number of
* times. Furthermore, each node is probed some number of times before moving
* onto the next one during each lap. The minimum latency gotten between nodes
* is kept as the latency between the nodes.
*
* After all that, the probe times are adjusted by normalizing values that are
* close to each other and local latencies are made the same. Lastly, the
* latencies are verified to make sure that certain conditions are met (eg.
* local < remote, latency(a, b) == latency(b, a), etc.).
*
* If any of the conditions aren't met, the code will export a NUMA
* configuration with the local CPUs and memory given by the SRAT or PCI config
* space registers and one remote memory latency since it can't tell exactly
* how far each node is from each other.
*/
void
lgrp_plat_probe(void)
{
int from;
int i;
int to;
if (!(lgrp_plat_probe_flags & LGRP_PLAT_PROBE_ENABLE) ||
return;
/* SRAT and SLIT should be enabled if DR operations are enabled. */
if (plat_dr_support_cpu() || plat_dr_support_memory())
return;
/*
* Determine ID of node containing current CPU
*/
/*
* Don't need to probe if got times already
*/
return;
/*
* Read vendor ID in Northbridge or read and write page(s)
* in each node from current CPU and remember how long it takes,
* so we can build latency topology of machine later.
* This should approximate the memory latency between each node.
*/
for (i = 0; i < lgrp_plat_probe_nrounds; i++) {
/*
* Get probe time and skip over any nodes that can't be
* probed yet or don't have memory
*/
if (probe_time == 0)
continue;
/*
* Keep lowest probe time as latency between nodes
*/
/*
* Update overall minimum and maximum probe times
* across all nodes
*/
}
}
/*
* Bail out if weren't able to probe any nodes from current CPU
*/
return;
/*
* - Fix up latencies such that local latencies are same,
* latency(i, j) == latency(j, i), etc. (if possible)
*
* - Verify that latencies look ok
*
* - Fallback to just optimizing for local and remote if
* latencies didn't look right
*/
}
/*
* Return platform handle for root lgroup
*/
lgrp_plat_root_hand(void)
{
return (LGRP_DEFAULT_HANDLE);
}
/*
* INTERNAL ROUTINES
*/
/*
* Update CPU to node mapping for given CPU and proximity domain.
* Return values:
* - zero for success
* - positive numbers for warnings
* - negative numbers for errors
*/
static int
{
uint_t i;
int node;
/*
* Get node number for proximity domain
*/
if (node == -1) {
domain);
if (node == -1)
return (-1);
}
/*
* Search for entry with given APIC ID and fill in its node and
* proximity domain IDs (if they haven't been set already)
*/
for (i = 0; i < nentries; i++) {
/*
* Skip nonexistent entries and ones without matching APIC ID
*/
continue;
/*
* Just return if entry completely and correctly filled in
* already
*/
return (1);
/*
* It's invalid to have more than one entry with the same
* local APIC ID in SRAT table.
*/
return (-2);
/*
* Fill in node and proximity domain IDs
*/
return (0);
}
/*
* It's possible that an apicid doesn't exist in the cpu_node map due
* to user limits number of CPUs powered on at boot by specifying the
* boot_ncpus kernel option.
*/
return (2);
}
/*
* Get node ID for given CPU
*/
static int
int cpu_node_nentries)
{
return (-1);
return (-1);
/*
* SRAT doesn't exist, isn't enabled, or there was an error processing
* it, so return node ID for Opteron and -1 otherwise.
*/
if (is_opteron())
return (-1);
}
/*
* Return -1 when CPU to node ID mapping entry doesn't exist for given
* CPU
*/
return (-1);
}
/*
*/
static int
{
/*
* Hash proximity domain ID into node to domain mapping table (array),
* search for entry with matching proximity domain ID, and return index
* of matching entry as node ID.
*/
do {
return (node);
}
return (-1);
}
/*
* Get NUMA configuration of machine
*/
static void
{
/*
* determine number of CPUs
*/
/*
* Determine which CPUs and memory are local to each other and number
* of NUMA nodes by reading ACPI System Resource Affinity Table (SRAT)
*/
if (lgrp_plat_apic_ncpus > 0) {
int retval;
/* Reserve enough resources if CPU DR is enabled. */
else
/*
* Temporarily allocate boot memory to use for CPU to node
* mapping since kernel memory allocator isn't alive yet
*/
sizeof (int));
if (lgrp_plat_cpu_node) {
sizeof (cpu_node_map_t));
} else {
}
/*
* Fill in CPU to node ID mapping table with APIC ID for each
* CPU
*/
if (retval <= 0) {
lgrp_plat_node_cnt = 1;
} else {
lgrp_plat_srat_error = 0;
}
}
/*
* Try to use PCI config space registers on Opteron if there's an error
* processing CPU to APIC ID mapping or SRAT
*/
if ((lgrp_plat_apic_ncpus <= 0 || lgrp_plat_srat_error != 0) &&
is_opteron())
/*
* Don't bother to setup system for multiple lgroups and only use one
* memory node when memory is interleaved between any nodes or there is
* only one NUMA node
*/
(void) lgrp_topo_ht_limit_set(1);
return;
}
/*
* processor chip. Tune lgrp_expand_proc_thresh and
* lgrp_expand_proc_diff so that lgrp_choose() will spread
* things out aggressively.
*/
/*
* There should be one memnode (physical page free list(s)) for
* each node if memory DR is disabled.
*/
/*
* Initialize min and max latency before reading SLIT or probing
*/
/*
* Determine how far each NUMA node is from each other by
* reading ACPI System Locality Information Table (SLIT) if it
* exists
*/
/*
* domains exist in system and either of following is true.
* 1) Failed to process SLIT table.
* 2) Latency probing is enabled by user.
*/
if (lgrp_plat_node_cnt > 1 &&
(plat_dr_support_cpu() || plat_dr_support_memory())) {
if (!lgrp_plat_slit_enable || lgrp_plat_slit_error != 0 ||
!lgrp_plat_srat_enable || lgrp_plat_srat_error != 0 ||
lgrp_plat_apic_ncpus <= 0) {
} else if (lgrp_plat_probe_flags & LGRP_PLAT_PROBE_ENABLE) {
"?lgrp: latency probing enabled by user, "
}
}
/* Done if succeeded to process SLIT table. */
if (lgrp_plat_slit_error == 0)
return;
/*
* Probe to determine latency between NUMA nodes when SLIT
* doesn't exist or make sense
*/
/*
* Specify whether to probe using vendor ID register or page copy
* if hasn't been specified already or is overspecified
*/
if (probe_op == 0 ||
if (is_opteron())
else
}
/*
* Probing errors can mess up the lgroup topology and
* force us fall back to a 2 level lgroup topology.
* Here we bound how tall the lgroup topology can grow
* in hopes of avoiding any anamolies in probing from
* messing up the lgroup topology by limiting the
* accuracy of the latency topology.
*
* Assume that nodes will at least be configured in a
* ring, so limit height of lgroup topology to be less
* than number of nodes on a system with 4 or more
* nodes
*/
}
/*
* Latencies must be within 1/(2**LGRP_LAT_TOLERANCE_SHIFT) of each other to
* be considered same
*/
/*
* Adjust latencies between nodes to be symmetric, normalize latencies between
* any nodes that are within some tolerance to be same, and make local
* latencies be same
*/
static void
{
int i;
int j;
int k;
int l;
u_longlong_t t;
/*
* Nothing to do when this is an UMA machine or don't have args needed
*/
if (max_mem_nodes == 1)
return;
probe_stats != NULL);
/*
* Make sure that latencies are symmetric between any two nodes
* (ie. latency(node0, node1) == latency(node1, node0))
*/
for (i = 0; i < lgrp_plat_node_cnt; i++) {
if (!memnode_info[i].exists)
continue;
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (!memnode_info[j].exists)
continue;
continue;
/*
* Latencies should be same
* - Use minimum of two latencies which should be same
* - Track suspect probe times not within tolerance of
* min value
* - Remember how much values are corrected by
*/
t = t2;
probe_stats->probe_suspect[i][j]++;
probe_stats->probe_suspect[j][i]++;
}
t = t1;
probe_stats->probe_suspect[i][j]++;
probe_stats->probe_suspect[j][i]++;
}
}
}
}
/*
* Keep track of which latencies get corrected
*/
for (i = 0; i < MAX_NODES; i++)
for (j = 0; j < MAX_NODES; j++)
lat_corrected[i][j] = 0;
/*
* For every two nodes, see whether there is another pair of nodes which
* are about the same distance apart and make the latencies be the same
* if they are close enough together
*/
for (i = 0; i < lgrp_plat_node_cnt; i++) {
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (!memnode_info[j].exists)
continue;
/*
* Pick one pair of nodes (i, j)
* and get latency between them
*/
/*
* Skip this pair of nodes if there isn't a latency
* for it yet
*/
if (t1 == 0)
continue;
for (k = 0; k < lgrp_plat_node_cnt; k++) {
for (l = 0; l < lgrp_plat_node_cnt; l++) {
if (!memnode_info[l].exists)
continue;
/*
* Pick another pair of nodes (k, l)
* not same as (i, j) and get latency
* between them
*/
if (k == i && l == j)
continue;
/*
* Skip this pair of nodes if there
* isn't a latency for it yet
*/
if (t2 == 0)
continue;
/*
* Skip nodes (k, l) if they already
* have same latency as (i, j) or
* their latency isn't close enough to
* be considered/made the same
*/
t1 >> lgrp_plat_probe_lt_shift) ||
continue;
/*
* Make latency(i, j) same as
* latency(k, l), try to use latency
* that has been adjusted already to get
* more consistency (if possible), and
* remember which latencies were
* adjusted for next time
*/
if (lat_corrected[i][j]) {
t = t1;
t2 = t;
} else if (lat_corrected[k][l]) {
t = t2;
t1 = t;
} else {
t = t2;
else
t = t1;
}
lat_corrected[i][j] =
lat_corrected[k][l] = 1;
}
}
}
}
/*
* Local latencies should be same
* - Find min and max local latencies
* - Make all local latencies be minimum
*/
min = -1;
max = 0;
for (i = 0; i < lgrp_plat_node_cnt; i++) {
if (!memnode_info[i].exists)
continue;
if (t == 0)
continue;
min = t;
if (t > max)
max = t;
}
for (i = 0; i < lgrp_plat_node_cnt; i++) {
int local;
if (!memnode_info[i].exists)
continue;
if (local == 0)
continue;
/*
* Track suspect probe times that aren't within
* tolerance of minimum local latency and how much
* probe times are corrected by
*/
probe_stats->probe_suspect[i][i]++;
/*
* Make local latencies be minimum
*/
}
}
/*
* Determine max probe time again since just adjusted latencies
*/
lat_stats->latency_max = 0;
for (i = 0; i < lgrp_plat_node_cnt; i++) {
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (!memnode_info[j].exists)
continue;
if (t > lat_stats->latency_max)
lat_stats->latency_max = t;
}
}
}
/*
* Verify following about latencies between nodes:
*
* - Latencies should be symmetric (ie. latency(a, b) == latency(b, a))
* - Local latencies same
* - Local < remote
* - Number of latencies seen is reasonable
* - Number of occurrences of a given latency should be more than 1
*
* Returns:
* 0 Success
* -1 Not symmetric
* -2 Local latencies not same
* -3 Local >= remote
*/
static int
{
int i;
int j;
/*
* Nothing to do when this is an UMA machine, lgroup topology is
* limited to 2 levels, or there aren't any probe times yet
*/
return (0);
/*
* Make sure that latencies are symmetric between any two nodes
* (ie. latency(node0, node1) == latency(node1, node0))
*/
for (i = 0; i < lgrp_plat_node_cnt; i++) {
if (!memnode_info[i].exists)
continue;
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (!memnode_info[j].exists)
continue;
continue;
return (-1);
}
}
/*
* Local latencies should be same
*/
for (i = 1; i < lgrp_plat_node_cnt; i++) {
if (!memnode_info[i].exists)
continue;
if (t2 == 0)
continue;
if (t1 == 0) {
continue;
}
return (-2);
}
/*
* Local latencies should be less than remote
*/
if (t1) {
for (i = 0; i < lgrp_plat_node_cnt; i++) {
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (!memnode_info[j].exists)
continue;
if (i == j || t2 == 0)
continue;
return (-3);
}
}
}
return (0);
}
/*
* Platform-specific initialization
*/
static void
lgrp_plat_main_init(void)
{
int curnode;
int ht_limit;
int i;
/*
* Print a notice that MPO is disabled when memory is interleaved
* across nodes....Would do this when it is discovered, but can't
* because it happens way too early during boot....
*/
if (lgrp_plat_mem_intrlv)
"MPO disabled because memory is interleaved\n");
/*
* Don't bother to do any probing if it is disabled, there is only one
* node, or the height of the lgroup topology less than or equal to 2
*/
if (!(lgrp_plat_probe_flags & LGRP_PLAT_PROBE_ENABLE) ||
/*
* Setup lgroup latencies for 2 level lgroup topology
* (ie. local and remote only) if they haven't been set yet
*/
return;
}
/*
* Should have been able to probe from CPU 0 when it was added
* to lgroup hierarchy, but may not have been able to then
* because it happens so early in boot that gethrtime() hasn't
* been initialized. (:-(
*/
return;
}
/*
* When probing memory, use one page for every sample to determine
* lgroup topology and taking multiple samples
*/
if (lgrp_plat_probe_mem_config.probe_memsize == 0)
/*
* Map memory in each node needed for probing to determine latency
* topology
*/
for (i = 0; i < lgrp_plat_node_cnt; i++) {
int mnode;
/*
* Skip this node and leave its probe page NULL
* if it doesn't have any memory
*/
mnode = i;
continue;
}
/*
* Allocate one kernel virtual page
*/
"lgrp_plat_main_init: couldn't allocate memory");
return;
}
/*
* Get PFN for first page in each node
*/
/*
* Map virtual page to first page in node
*/
}
/*
* Probe from current CPU
*/
}
/*
* Return the number of free, allocatable, or installed
* pages in an lgroup
* This is a copy of the MAX_MEM_NODES == 1 version of the routine
* used when MPO is disabled (i.e. single lgroup) or this is the root lgroup
*/
static pgcnt_t
{
extern struct memlist *phys_avail;
extern struct memlist *phys_install;
switch (query) {
case LGRP_MEM_SIZE_FREE:
case LGRP_MEM_SIZE_AVAIL:
return (npgs);
case LGRP_MEM_SIZE_INSTALL:
return (npgs);
default:
return ((pgcnt_t)0);
}
}
/*
* Update node to proximity domain mappings for given domain and return node ID
*/
static int
{
/*
* Hash proximity domain ID into node to domain mapping table (array)
* and add entry for it into first non-existent or matching entry found
*/
do {
/*
* Entry doesn't exist yet, so create one for this proximity
* domain and return node ID which is index into mapping table.
*/
return (node);
}
/*
* Entry exists for this proximity domain already, so just
* return node ID (index into table).
*/
return (node);
/*
* Ran out of supported number of entries which shouldn't happen....
*/
return (-1);
}
/*
* Update node memory information for given proximity domain with specified
* starting and ending physical address range (and return positive numbers for
* success and negative ones for errors)
*/
static int
{
/*
* Get node number for proximity domain
*/
if (node == -1) {
domain);
if (node == -1)
return (-1);
}
/*
* This function is called during boot if device_id is
* ACPI_MEMNODE_DEVID_BOOT, otherwise it's called at runtime for
* memory DR operations.
*/
if (device_id != ACPI_MEMNODE_DEVID_BOOT) {
for (mnode = lgrp_plat_node_cnt;
return (1);
}
}
if (lgrp_plat_max_mem_node >= memnode_cnt) {
return (-3);
} else {
return (0);
}
}
/*
* Create entry in table for node if it doesn't exist
*/
return (0);
}
/*
* Entry already exists for this proximity domain
*
* There may be more than one SRAT memory entry for a domain, so we may
* need to update existing start or end address for the node.
*/
return (1);
}
return (-2);
}
/*
* Have to sort nodes by starting physical address because plat_mnode_xcheck()
* assumes and expects memnodes to be sorted in ascending order by physical
* address.
*/
static void
{
int i;
int j;
int n;
return;
/*
* Sorted already?
*/
for (i = 0; i < node_cnt - 1; i++) {
/*
* Skip entries that don't exist
*/
if (!memnode_info[i].exists)
continue;
/*
* Try to find next existing entry to compare against
*/
for (j = i + 1; j < node_cnt; j++) {
if (memnode_info[j].exists) {
break;
}
}
/*
* Done if no more existing entries to compare against
*/
break;
/*
* Not sorted if starting address of current entry is bigger
* than starting address of next existing entry
*/
break;
}
}
/*
* Don't need to sort if sorted already
*/
return;
/*
* Just use bubble sort since number of nodes is small
*/
n = node_cnt;
do {
n--;
for (i = 0; i < n; i++) {
/*
* Skip entries that don't exist
*/
if (!memnode_info[i].exists)
continue;
/*
* Try to find next existing entry to compare against
*/
for (j = i + 1; j <= n; j++) {
if (memnode_info[j].exists) {
break;
}
}
/*
* Done if no more existing entries to compare against
*/
break;
/*
* Swap node to proxmity domain ID assignments
*/
sizeof (node_domain_map_t));
sizeof (node_domain_map_t));
sizeof (node_domain_map_t));
/*
* Swap node to physical memory assignments
*/
sizeof (memnode_phys_addr_map_t));
sizeof (memnode_phys_addr_map_t));
sizeof (memnode_phys_addr_map_t));
}
}
/*
* Check to make sure that CPUs assigned to correct node IDs now since
* node to proximity domain ID assignments may have been changed above
*/
return;
for (i = 0; i < cpu_count; i++) {
int node;
cpu_node[i].prox_domain);
}
}
/*
* Return time needed to probe from current CPU to memory in given node
*/
static hrtime_t
{
int from;
int i;
int ipl;
extern int use_sse_pagecopy;
/*
* Determine ID of node containing current CPU
*/
/*
* Do common work for probing main memory
*/
/*
* Skip probing any nodes without memory and
* set probe time to 0
*/
return (0);
}
/*
* Invalidate caches once instead of once every sample
* which should cut cost of probing by a lot
*/
}
/*
* Probe from current CPU to given memory using specified operation
* and take specified number of samples
*/
max = 0;
min = -1;
for (i = 0; i < lgrp_plat_probe_nsamples; i++) {
/*
* Can't measure probe time if gethrtime() isn't working yet
*/
return (0);
/*
* Measure how long it takes to read vendor ID from
* Northbridge
*/
} else {
/*
* Measure how long it takes to copy page
* on top of itself
*/
if (use_sse_pagecopy)
else
}
}
/*
* Update minimum and maximum probe times between
* these two nodes
*/
return (min);
}
/*
* Read boot property with CPU to APIC ID array, fill in CPU to node ID
* mapping table with APIC ID for each CPU (if pointer to table isn't NULL),
* and return number of CPU APIC IDs.
*
* NOTE: This code assumes that CPU IDs are assigned in order that they appear
* in in cpu_apicid_array boot property which is based on and follows
* same ordering as processor list in ACPI MADT. If the code in
* CPU IDs ever changes, then this code will need to change too....
*/
static int
{
int boot_prop_len;
int i;
int n;
/*
* Check length of property value
*/
if (boot_prop_len <= 0)
return (-1);
/*
* Calculate number of entries in array and return when the system is
* not very interesting for NUMA. It's not interesting for NUMA if
* system has only one CPU and doesn't support CPU hotplug.
*/
n = boot_prop_len / sizeof (*cpu_apicid_array);
if (n == 1 && !plat_dr_support_cpu())
return (-2);
sizeof (*cpu_apicid_array));
/*
* Get CPU to APIC ID property value
*/
if (cpu_apicid_array == NULL ||
return (-3);
/*
* Just return number of CPU APIC IDs if CPU to node mapping table is
* NULL
*/
if (plat_dr_support_cpu() && n >= boot_ncpus) {
return (boot_ncpus);
} else {
return (n);
}
}
/*
* Fill in CPU to node ID mapping table with APIC ID for each CPU
*/
for (i = 0; i < n; i++) {
/* Only add boot CPUs into the map if CPU DR is enabled. */
if (plat_dr_support_cpu() && i >= boot_ncpus)
break;
}
/*
* Return number of CPUs based on number of APIC IDs
*/
return (i);
}
/*
* Read ACPI System Locality Information Table (SLIT) to determine how far each
* NUMA node is from each other
*/
static int
{
int i;
int j;
int src;
int dst;
int localities;
int retval;
return (1);
return (2);
/*
* Fill in latency matrix based on SLIT entries
*/
for (i = 0; i < localities; i++) {
node_cnt, i);
if (src == -1)
continue;
for (j = 0; j < localities; j++) {
node_cnt, j);
if (dst == -1)
continue;
}
}
/*
*/
if (retval) {
/*
* Reinitialize (zero) latency table since SLIT doesn't look
* right
*/
for (i = 0; i < localities; i++) {
for (j = 0; j < localities; j++)
}
} else {
/*
* Update min and max latencies seen since SLIT looks valid
*/
}
return (retval);
}
/*
* Update lgrp latencies according to information returned by ACPI _SLI method.
*/
static int
{
int i;
return (-1);
if (src == -1) {
if (src == -1)
return (-1);
}
/*
* Don't update latency info if topology has been flattened to 2 levels.
*/
if (lgrp_plat_topo_flatten != 0) {
return (0);
}
/*
* Latency information for proximity domain is ready.
* TODO: support adjusting latency information at runtime.
*/
return (0);
}
/* Validate latency information. */
for (i = 0; i < sli_cnt; i++) {
if (i == domain_id) {
if (sli_info[i] != ACPI_SLIT_SELF_LATENCY ||
return (-1);
}
} else {
if (sli_info[i] <= ACPI_SLIT_SELF_LATENCY ||
return (-1);
}
}
}
for (i = 0; i < sli_cnt; i++) {
if (dst == -1)
continue;
/* Update row in latencies matrix. */
/* Update column in latencies matrix. */
}
return (0);
}
/*
* Read ACPI System Resource Affinity Table (SRAT) to determine which CPUs
* and memory are local to each other in the same NUMA node and return number
* of nodes
*/
static int
{
int i;
int node_cnt;
int proc_entry_count;
int rc;
/*
* Nothing to do when no SRAT or disabled
*/
return (-1);
/*
* Try to get domain information from MSCT table.
* ACPI4.0: OSPM will use information provided by the MSCT only
* when the System Resource Affinity Table (SRAT) exists.
*/
if (node_cnt <= 0) {
/*
* Determine number of nodes by counting number of proximity
* domains in SRAT.
*/
}
/*
* Return if number of nodes is 1 or less since don't need to read SRAT.
*/
if (node_cnt == 1)
return (1);
else if (node_cnt <= 0)
return (-2);
/*
* Walk through SRAT, examining each CPU and memory entry to determine
* which CPUs and memory belong to which node.
*/
proc_entry_count = 0;
case ACPI_SRAT_TYPE_CPU_AFFINITY: { /* CPU entry */
break;
/*
* Calculate domain (node) ID and fill in APIC ID to
*/
for (i = 0; i < 3; i++) {
((i + 1) * 8);
}
if (rc < 0)
return (-3);
else if (rc == 0)
break;
}
case ACPI_SRAT_TYPE_MEMORY_AFFINITY: { /* memory entry */
memnode_info == NULL)
break;
/*
* to memory mapping table
*/
/*
* According to ACPI 4.0, both ENABLE and HOTPLUG flags
* may be set for memory address range entries in SRAT
* table which are reserved for memory hot plug.
* We intersect memory address ranges in SRAT table
* with memory ranges in physinstalled to filter out
* memory address ranges reserved for hot plug.
*/
continue;
}
/* Skip this entry if no memory installed. */
break;
}
return (-4);
break;
}
case ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY: { /* x2apic CPU */
break;
/*
* Calculate domain (node) ID and fill in APIC ID to
*/
if (rc < 0)
return (-3);
else if (rc == 0)
break;
}
default:
break;
}
}
/*
* Should have seen at least as many SRAT processor entries as CPUs
*/
if (proc_entry_count < cpu_count)
return (-5);
/*
* Need to sort nodes by starting physical address since VM system
* assumes and expects memnodes to be sorted in ascending order by
* physical address
*/
return (node_cnt);
}
/*
* Allocate permanent memory for any temporary memory that we needed to
* allocate using BOP_ALLOC() before kmem_alloc() and VM system were
* initialized and copy everything from temporary to permanent memory since
* temporary boot memory will eventually be released during boot
*/
static void
{
void *buf;
if (lgrp_plat_cpu_node_nentries > 0) {
}
}
/*
* Return number of proximity domains given in ACPI SRAT
*/
static int
{
int domain_cnt;
int i;
return (1);
/*
* Walk through SRAT to find minimum proximity domain ID
*/
case ACPI_SRAT_TYPE_CPU_AFFINITY: { /* CPU entry */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
for (i = 0; i < 3; i++) {
((i + 1) * 8);
}
break;
}
case ACPI_SRAT_TYPE_MEMORY_AFFINITY: { /* memory entry */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
break;
}
case ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY: { /* x2apic CPU */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
break;
}
default:
continue;
}
/*
* Keep track of minimum proximity domain ID
*/
if (domain < domain_min)
domain_min = domain;
}
/*
* Walk through SRAT, examining each CPU and memory entry to determine
* proximity domain ID for each.
*/
domain_cnt = 0;
case ACPI_SRAT_TYPE_CPU_AFFINITY: { /* CPU entry */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
for (i = 0; i < 3; i++) {
((i + 1) * 8);
}
break;
}
case ACPI_SRAT_TYPE_MEMORY_AFFINITY: { /* memory entry */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
break;
}
case ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY: { /* x2apic CPU */
item = (ACPI_SUBTABLE_HEADER *)
continue;
}
break;
}
default:
continue;
}
/*
* Count and keep track of which proximity domain IDs seen
*/
do {
/*
* Create entry for proximity domain and increment
* count when no entry exists where proximity domain
* hashed
*/
if (!node_domain[i].exists) {
domain_cnt++;
break;
}
/*
* Nothing to do when proximity domain seen already
* and its entry exists
*/
break;
}
/*
* Entry exists where proximity domain hashed, but for
* different proximity domain so keep search for empty
* slot to put it or matching entry whichever comes
* first.
*/
i = (i + 1) % MAX_NODES;
} while (i != start);
/*
* Didn't find empty or matching entry which means have more
* proximity domains than supported nodes (:-(
*/
return (-1);
}
return (domain_cnt);
}
/*
* Parse domain information in ACPI Maximum System Capability Table (MSCT).
* MSCT table has been verified in function process_msct() in fakebop.c.
*/
static int
{
int last_seen = 0;
return (-1);
"?lgrp: too many proximity domains (%d), max %d supported, "
return (-1);
}
if (prox_domain_min != NULL) {
}
/*
* Break out if all proximity domains have been
* processed. Some BIOSes may have unused items
* at the end of MSCT table.
*/
break;
}
}
}
}
/*
* Set lgroup latencies for 2 level lgroup topology
*/
static void
{
int i, j;
if (lgrp_plat_node_cnt >= 4)
"MPO only optimizing for local and remote\n");
for (i = 0; i < lgrp_plat_node_cnt; i++) {
for (j = 0; j < lgrp_plat_node_cnt; j++) {
if (i == j)
else
}
}
/* TODO: check it. */
}
/*
* The following Opteron specific constants, macros, types, and routines define
* PCI configuration space registers and how to read them to determine the NUMA
* configuration of *supported* Opteron processors. They provide the same
* information that may be gotten from the ACPI System Resource Affinity Table
* (SRAT) if it exists on the machine of interest.
*
* The AMD BIOS and Kernel Developer's Guide (BKDG) for the processor family
* of interest describes all of these registers and their contents. The main
* registers used by this code to determine the NUMA configuration of the
* machine are the node ID register for the number of NUMA nodes and the DRAM
* address map registers for the physical address range of each node.
*
* NOTE: The format and how to determine the NUMA configuration using PCI
* config space registers may change or may not be supported in future
* Opteron processor families.
*/
/*
* How many bits to shift Opteron DRAM Address Map base and limit registers
* to get actual value
*/
/*
* Macros to derive addresses from Opteron DRAM Address Map registers
*/
/*
* Bit masks defining what's in Opteron DRAM Address Map base register
*/
/*
* Bit masks defining what's in Opteron DRAM Address Map limit register
*/
/*
* Opteron Node ID register in PCI configuration space contains
* number of nodes in system, etc. for Opteron K8. The following
* constants and macros define its contents, structure, and access.
*/
/*
* Bit masks defining what's in Opteron Node ID register
*/
/*
* How many bits in Opteron Node ID register to shift right to get actual value
*/
/*
* Macros to get values from Opteron Node ID register
*/
/*
* Macro to setup PCI Extended Configuration Space (ECS) address to give to
*
* NOTE: Should only be used in lgrp_plat_init() before MMIO setup because any
* other uses should just do MMIO to access PCI ECS.
* Must enable special bit in Northbridge Configuration Register on
* Greyhound for extended CF8 space access to be able to access PCI ECS
* accessing PCI ECS.
*/
/*
* PCI configuration space registers accessed by specifying
* a bus, device, function, and offset. The following constants
* define the values needed to access Opteron K8 configuration
* info to determine its node topology
*/
/*
* Opteron PCI configuration space register function values
*/
/*
* PCI Configuration Space register offsets
*/
/*
* Opteron PCI Configuration Space device IDs for nodes
*/
/*
* Opteron DRAM address map gives base and limit for physical memory in a node
*/
typedef struct opt_dram_addr_map {
/*
* Supported AMD processor families
*/
/*
* Whether to have is_opteron() return 1 even when processor isn't supported
*/
/*
* AMD processor family for current CPU
*/
/*
* Determine whether we're running on a supported AMD Opteron since reading
* node count and DRAM address map registers may have different format or
* may not be supported across processor families
*/
static int
is_opteron(void)
{
if (x86_vendor != X86_VENDOR_AMD)
return (0);
if (opt_family == AMD_FAMILY_HAMMER ||
return (1);
else
return (0);
}
/*
* Determine NUMA configuration for Opteron from registers that live in PCI
* configuration space
*/
static void
{
/*
* Read configuration registers from PCI configuration space to
* determine node information, which memory is in each node, etc.
*
* Write to PCI configuration space address register to specify
*/
/*
* Read node ID register for node 0 to get node count
*/
/*
* If number of nodes is more than maximum supported, then set node
* count to 1 and treat system as UMA instead of NUMA.
*/
*node_cnt = 1;
return;
}
/*
* For Greyhound, PCI Extended Configuration Space must be enabled to
* read high DRAM address map base and limit registers
*/
if (opt_family == AMD_FAMILY_GREYHOUND) {
if ((nb_cfg_reg & AMD_GH_NB_CFG_EN_ECS) == 0)
}
/*
* Read node ID register (except for node 0 which we just read)
*/
if (node > 0) {
}
/*
* Read DRAM base and limit registers which specify
* physical memory range of each node
*/
if (opt_family != AMD_FAMILY_GREYHOUND)
base_hi = 0;
else {
}
if (opt_family != AMD_FAMILY_GREYHOUND)
limit_hi = 0;
else {
}
/*
* Increment device number to next node and register offsets
* for DRAM base register of next node
*/
off_hi += 4;
off_lo += 4;
dev++;
/*
* Both read and write enable bits must be enabled in DRAM
* address map base register for physical memory to exist in
* node
*/
if ((base_lo & OPT_DRAMBASE_LO_MASK_RE) == 0 ||
(base_lo & OPT_DRAMBASE_LO_MASK_WE) == 0) {
/*
* Mark node memory as non-existent and set start and
* end addresses to be same in memnode_info[]
*/
(pfn_t)-1;
continue;
}
/*
* Mark node memory as existing and remember physical address
* range of each node for use later
*/
}
/*
* Restore PCI Extended Configuration Space enable bit
*/
if (opt_family == AMD_FAMILY_GREYHOUND) {
if ((nb_cfg_reg & AMD_GH_NB_CFG_EN_ECS) == 0)
}
}
/*
* Return average amount of time to read vendor ID register on Northbridge
* N times on specified destination node from current CPU
*/
static hrtime_t
{
int cnt;
/* LINTED: set but not used in function */
int ipl;
return (elapsed);
}