mp_platform_common.c revision 2df1fe9ca32bb227b9158c67f5c00b54c20b10fd
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
* PSMI 1.6 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_6
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
/*
* Local Function Prototypes
*/
static int apic_handle_defconf();
static int apic_find_bus_type(char *bus);
static int apic_find_bus(int busid);
static int apic_find_bus_id(int bustype);
static void apic_xlate_vector_free_timeout_handler(void *arg);
struct ioapic_reprogram_data *drep);
int type);
static void delete_defer_repro_ent(int which_irq);
static void apic_ioapic_wait_pending_clear(int ioapicindex,
int intin_no);
int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
/* ACPI SCI interrupt configuration; -1 if SCI not used */
int apic_sci_vect = -1;
/*
* psm name pointer
*/
static char *psm_name;
/* ACPI support routines */
static int acpi_probe(char *);
/*
*/
/* Max wait time (in repetitions) for flags to clear in an RDT entry. */
int apic_max_reps_clear_pending = 1000;
/* The irq # is implicit in the array index: */
/*
* APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info
* is indexed by IRQ number, NOT by vector number.
*/
/* start with cpu 1 */
/*
* If enabled, the distribution works as follows:
* On every interrupt entry, the current ipl for the CPU is set in cpu_info
* and the irq corresponding to the ipl is also set in the aci_current array.
* interrupt exit and setspl (due to soft interrupts) will cause the current
* ipl to be be changed. This is cache friendly as these frequently used
* paths write into a per cpu structure.
*
* Sampling is done by checking the structures for all CPUs and incrementing
* the busy field of the irq (if any) executing on each CPU and the busy field
* of the corresponding CPU.
* In periodic mode this is done on every clock interrupt.
* In one-shot mode, this is done thru a cyclic with an interval of
* apic_redistribute_sample_interval (default 10 milli sec).
*
* Every apic_sample_factor_redistribution times we sample, we do computations
* to decide which interrupt needs to be migrated (see comments
* before apic_intr_redistribute().
*/
/*
* Following 3 variables start as % and can be patched or set using an
* API to be defined in future. They will be scaled to
* sample_factor_redistribution which is in turn set to hertz+1 (in periodic
* mode), or 101 in one-shot mode to stagger it away from one sec processing
*/
int apic_int_busy_mark = 60;
int apic_int_free_mark = 20;
int apic_diff_for_redistribution = 10;
/* sampling interval for interrupt redistribution for dynamic migration */
/*
* number of times we sample before deciding to redistribute interrupts
* for dynamic migration
*/
int apic_sample_factor_redistribution = 101;
/* timeout for xlate_vector, mark_vector */
int apic_redist_cpu_skip = 0;
int apic_num_imbalance = 0;
int apic_num_rebind = 0;
int apic_nproc = 0;
size_t apic_cpus_size = 0;
int apic_defconf = 0;
int apic_irq_translate = 0;
int apic_spec_rev = 0;
int apic_imcrp = 0;
int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
/*
* For interrupt link devices, if apic_unconditional_srs is set, an irq resource
* will be assigned (via _SRS). If it is not set, use the current
* irq setting (via _CRS), but only if that irq is in the set of possible
* irqs (returned by _PRS) for the device.
*/
int apic_unconditional_srs = 1;
/*
* For interrupt link devices, if apic_prefer_crs is set when we are
* assigning an IRQ resource to a device, prefer the current IRQ setting
* over other possible irq settings under same conditions.
*/
int apic_prefer_crs = 1;
/*
* First available slot to be used as IRQ index into the apic_irq_table
* for those interrupts (like MSI/X) that don't have a physical IRQ.
*/
/*
* apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
* and bound elements of cpus_info and the temp_cpu element of irq_struct
*/
/*
* apic_defer_reprogram_lock ensures that only one processor is handling
* deferred interrupt programming at *_intr_exit time.
*/
static lock_t apic_defer_reprogram_lock;
/*
* The current number of deferred reprogrammings outstanding
*/
#ifdef DEBUG
/*
* Counters that keep track of deferred reprogramming stats
*/
#endif
static int apic_io_max = 0; /* no. of i/o apics enabled */
static struct apic_io_intr *apic_io_intrp = 0;
static uint32_t eisa_level_intr_mask = 0;
/* At least MSB will be set if EISA bus */
static int apic_pci_bus_total = 0;
static uchar_t apic_single_pci_busid = 0;
/*
* airq_mutex protects additions to the apic_irq_table - the first
* pointer and any airq_nexts off of that one. It also protects
* apic_max_device_irq & apic_min_device_irq. It also guarantees
* that share_id is unique as new ids are generated only when new
* irq_t structs are linked in. Once linked in the structs are never
* deleted. temp_cpu & mps_intr_index field indicate if it is programmed
* or allocated. Note that there is a slight gap between allocating in
* apic_introp_xlate and programming in addspl.
*/
int apic_max_device_irq = 0;
/*
* Following declarations are for revectoring; used when ISRs at different
* IPLs share an irq.
*/
static lock_t apic_revector_lock;
int apic_revector_pending = 0;
static uchar_t *apic_oldvec_to_newvec;
static uchar_t *apic_newvec_to_oldvec;
typedef struct prs_irq_list_ent {
int list_prio;
struct prs_irq_list_ent *next;
/*
* ACPI variables
*/
/* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
int apic_enable_acpi = 0;
/* ACPI Multiple APIC Description Table ptr */
/* ACPI Interrupt Source Override Structure ptr */
static int acpi_iso_cnt = 0;
/* ACPI Non-maskable Interrupt Sources ptr */
static int acpi_nmi_scnt = 0;
static int acpi_nmi_ccnt = 0;
/*
* The following added to identify a software poweroff method if available.
*/
static struct {
int poweroff_method;
} apic_mps_ids[] = {
};
/*
* Auto-configuration routines
*/
/*
* Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
* May work with 1.1 - but not guaranteed.
* According to the MP Spec, the MP floating pointer structure
* will be searched in the order described below:
* 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
* 2. Within the last kilobyte of system base memory
* 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
* Once we find the right signature with proper checksum, we call
* either handle_defconf or parse_mpct to get all info necessary for
* subsequent operations.
*/
int
apic_probe_common(char *modname)
{
struct apic_mpfps_hdr *fpsp;
struct apic_mp_cnf_hdr *hdrp;
int acpi_user_options;
if (apic_forceload < 0)
return (retval);
/*
* Remember who we are
*/
/* Allow override for MADT-only mode */
"acpi-user-options", 0);
/* Allow apic_use_acpi to override MADT-only mode */
if (!apic_use_acpi)
/*
* mapin the bios data area 40:0
* 40:13h - two-byte location reports the base memory size
* 40:0Eh - two-byte location for the exact starting address of
* the EBDA segment for EISA
*/
if (!biosdatap)
return (retval);
/*LINTED: pointer cast may result in improper alignment */
/* check the 1k of EBDA */
if (ebda_seg) {
if (fptr) {
if (!(fpsp =
}
}
/* If not in EBDA, check the last k of system base memory */
if (!fpsp) {
/*LINTED: pointer cast may result in improper alignment */
if (base_mem_size > 512)
else
/* if ebda == last k of base mem, skip to check BIOS ROM */
if (base_mem_end != ebda_start) {
if (fptr) {
}
}
}
/* If still cannot find it, check the BIOS ROM space */
if (!fpsp) {
if (fptr) {
if (!(fpsp =
return (retval);
}
}
}
return (retval);
}
return (retval);
}
/* check IMCR is present or not */
/* check default configuration (dual CPUs) */
return (apic_handle_defconf());
}
/* MP Configuration Table */
/*
* Map in enough memory for the MP Configuration Table Header.
* Use this table to read the total length of the BIOS data and
* map in all the info
*/
/*LINTED: pointer cast may result in improper alignment */
sizeof (struct apic_mp_cnf_hdr), PROT_READ);
if (!hdrp)
return (retval);
/* check mp configuration table signature PCMP */
return (retval);
}
/* This is an ACPI machine No need for further checks */
return (retval);
}
/*
* Map in the entries for this machine, ie. Processor
* Entry Tables, Bus Entry Tables, etc.
* They are in fixed order following one another
*/
if (!mpct)
return (retval);
goto apic_fail1;
/*LINTED: pointer cast may result in improper alignment */
if (!apicadr)
goto apic_fail1;
/* Parse all information in the tables */
return (PSM_SUCCESS);
for (i = 0; i < apic_io_max; i++)
if (apic_cpus)
if (apicadr)
return (retval);
}
static void
{
int i;
for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
i++) {
break;
}
}
if (apic_debug_mps_id != 0) {
"Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
hdrp->mpcnf_oem_str[0],
hdrp->mpcnf_prod_str[0],
}
}
static int
acpi_probe(char *modname)
{
int acpi_verboseflags = 0;
int sci;
int apic_ix;
if (!apic_use_acpi)
return (PSM_FAILURE);
return (PSM_FAILURE);
if (!apicadr)
return (PSM_FAILURE);
CPUSET_ONLY(apic_cpumask, 0);
apic_io_max = 0;
madt_seen = sizeof (*acpi_mapic_dtp);
case APIC_PROCESSOR:
if (mpa->ProcessorEnabled) {
acpica_map_cpu(0, mpa);
} else if (apic_nproc < NCPU) {
index++;
apic_nproc++;
} else
"maximum no. of CPUs (= %d)",
}
break;
case APIC_IO:
if (apic_io_max < MAX_IO_APIC) {
if (!ioapic)
goto cleanup;
apic_io_max++;
}
break;
case APIC_XRUPT_OVERRIDE:
acpi_iso_cnt++;
break;
case APIC_NMI:
/* UNIMPLEMENTED */
if (acpi_nmi_sp == NULL)
acpi_nmi_sp = mns;
mns->TriggerMode);
break;
case APIC_LOCAL_NMI:
/* UNIMPLEMENTED */
if (acpi_nmi_cp == NULL)
acpi_nmi_cp = mlan;
break;
case APIC_ADDRESS_OVERRIDE:
/* UNIMPLEMENTED */
break;
case APIC_IO_SAPIC:
/* UNIMPLEMENTED */
break;
case APIC_XRUPT_SOURCE:
/* UNIMPLEMENTED */
"!apic: irq source: %d %d %d %d %d %d %d\n",
mis->IoSapicVector);
break;
default:
break;
}
/* advance to next entry */
}
goto cleanup;
/*
* ACPI doesn't provide the local apic ver, get it directly from the
* local apic
*/
for (i = 0; i < apic_nproc; i++) {
}
for (i = 0; i < apic_io_max; i++) {
apic_ix = i;
/*
* need to check Sitka on the following acpi problem
* On the Sitka, the ioapic's apic_id field isn't reporting
* the actual io apic id. We have reported this problem
* to Intel. Until they fix the problem, we will get the
* actual id directly from the ioapic.
*/
if (hid != apic_io_id[i]) {
if (apic_io_id[i] == 0)
apic_io_id[i] = hid;
else { /* set ioapic id to whatever reported by ACPI */
}
}
if (apic_first_avail_irq <= apic_io_vectend[i])
}
/*
* Process SCI configuration here
* An error may be returned here if
* acpi-user-options specifies legacy mode
* (no SCI, no ACPI mode)
*/
sci = -1;
/*
* Now call acpi_init() to generate namespaces
* If this fails, we don't attempt to use ACPI
* even if we were able to get a MADT above
*/
if (acpica_init() != AE_OK)
goto cleanup;
/*
* Call acpica_build_processor_map() now that we have
* ACPI namesspace access
*/
/*
* Squirrel away the SCI and flags for later on
* in apic_picinit() when we're ready
*/
apic_sci_vect = sci;
goto cleanup;
/* Enable ACPI APIC interrupt routing */
apic_enable_acpi = 1;
if (apic_use_acpi_madt_only) {
}
return (PSM_SUCCESS);
}
/* if setting APIC mode failed above, we fall through to cleanup */
}
apic_nproc = 0;
for (i = 0; i < apic_io_max; i++) {
}
apic_io_max = 0;
acpi_iso_cnt = 0;
acpi_nmi_sp = NULL;
acpi_nmi_scnt = 0;
acpi_nmi_cp = NULL;
acpi_nmi_ccnt = 0;
return (PSM_FAILURE);
}
/*
* Handle default configuration. Fill in reqd global variables & tables
* Fill all details as MP table does not give any more info
*/
static int
{
/*LINTED: pointer cast may result in improper alignment */
/*LINTED: pointer cast may result in improper alignment */
apic_cpus = (apic_cpus_info_t *)
goto apic_handle_defconf_fail;
CPUSET_ONLY(apic_cpumask, 0);
apic_nproc = 2;
/*
* According to the PC+MP spec 1.1, the local ids
* for the default configuration has to be 0 or 1
*/
else if (apic_cpus[0].aci_local_id == 0)
else
goto apic_handle_defconf_fail;
apic_io_id[0] = 2;
apic_io_max = 1;
if (apic_defconf >= 5) {
} else {
apic_io_ver[0] = 0;
}
return (PSM_SUCCESS);
if (apic_cpus)
if (apicadr)
if (apicioadr[0])
return (PSM_FAILURE);
}
/* Parse the entries in MP configuration table and collect info that we need */
static int
{
struct apic_procent *procp;
struct apic_io_entry *ioapicp;
struct apic_io_intr *intrp;
int apic_ix;
/*LINTED: pointer cast may result in improper alignment */
/* No need to count cpu entries if we won't use them */
if (!bypass_cpus_and_ioapics) {
/* Find max # of CPUS and allocate structure accordingly */
apic_nproc = 0;
if (apic_nproc < NCPU)
apic_nproc++;
}
procp++;
}
if (apic_nproc > NCPU)
return (PSM_FAILURE);
}
/*LINTED: pointer cast may result in improper alignment */
/*
* start with index 1 as 0 needs to be filled in with Boot CPU, but
* if we're bypassing this information, it has already been filled
* in by acpi_probe(), so don't overwrite it.
*/
if (!bypass_cpus_and_ioapics)
apic_nproc = 1;
/* check whether the cpu exists or not */
if (!bypass_cpus_and_ioapics &&
if (apic_cpus[0].aci_local_id !=
return (PSM_FAILURE);
}
apic_cpus[0].aci_local_ver =
} else {
apic_nproc++;
}
}
procp++;
}
/*
* Save start of bus entries for later use.
* Get EISA level cntrl if EISA bus is present.
* Also get the CPI bus id for single CPI bus case
*/
/*
* apic_single_pci_busid will be used only if
* apic_pic_bus_total is equal to 1
*/
}
busp++;
}
if (!bypass_cpus_and_ioapics)
apic_io_max = 0;
do {
/*LINTED: pointer cast may result in improper alignment */
if (!apicioadr[apic_io_max])
return (PSM_FAILURE);
if (apic_io_id[apic_io_max] == 0)
else {
/*
* set ioapic id to whatever
* reported by MPS
*
* may not need to set index
* again ???
* take it out and try
*/
apic_io_id[apic_io_max]) <<
24;
APIC_ID_CMD, id);
}
}
apic_io_max++;
}
}
ioapicp++;
apic_irq_translate = 1;
break;
}
intrp++;
}
return (PSM_SUCCESS);
}
apic_cpu_in_range(int cpu)
{
}
{
int i;
uchar_t min_io_apic_ver = 0;
/*
* Don't assume all IO APICs in the system are the same.
*
* Set to the minimum version.
*/
for (i = 0; i < apic_io_max; i++) {
if ((apic_io_ver[i] != 0) &&
((min_io_apic_ver == 0) ||
(min_io_apic_ver >= apic_io_ver[i])))
min_io_apic_ver = apic_io_ver[i];
}
/* Assume all local APICs are of the same version. */
}
return (version);
}
static struct apic_mpfps_hdr *
{
int i;
/* Look for the pattern "_MP_" */
for (i = 0; i < len; i += 16) {
if ((*(cptr+i) == '_') &&
/*LINTED: pointer cast may result in improper alignment */
return ((struct apic_mpfps_hdr *)(cptr + i));
}
return (NULL);
}
static int
{
int i;
cksum = 0;
for (i = 0; i < len; i++)
return ((int)cksum);
}
/*
* Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable
* are also set to NULL. vector->irq is set to a value which cannot map
* to a real irq to show that it is free.
*/
void
{
int i, j, indx;
int *iptr;
/*
* Initialize apic_ipls from apic_vectortoipl. This array is
* used in apic_intr_enter to determine the IPL to use for the
* corresponding vector. On some systems, due to hardware errata
* and interrupt sharing, the IPL may not correspond to the IPL listed
* in apic_vectortoipl (see apic_addspl and apic_delspl).
*/
for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
indx = i * APIC_VECTOR_PER_IPL;
for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++)
}
/* cpu 0 is always up (for now) */
iptr = (int *)&apic_irq_table[0];
for (i = 0; i <= APIC_MAX_VECTOR; i++) {
apic_level_intr[i] = 0;
/* These *must* be initted to B_TRUE! */
apic_reprogram_info[i].tries = 0;
apic_reprogram_info[i].bindcpu = 0;
}
/*
* Allocate a dummy irq table entry for the reserved entry.
* This takes care of the race between removing an irq and
* clock detecting a CPU in that irq during interrupt load
* sampling.
*/
}
void
{
int apic_ix;
int i, j;
/* mask interrupt vectors */
for (j = 0; j < apic_io_max && mask_apic; j++) {
int intin_max;
apic_ix = j;
/* Bits 23-16 define the maximum redirection entries */
for (i = 0; i < intin_max; i++)
}
/*
*/
if (apic_sci_vect > 0) {
/*
* acpica has already done add_avintr(); we just
* to finish the job by mimicing translate_irq()
*
* Fake up an intrspec and setup the tables
*/
return;
}
iflag = intr_clear();
/* Program I/O APIC */
irqptr->airq_share++;
}
}
/*
* Add mask bits to disable interrupt vector from happening
* at or above IPL. In addition, it should remove mask bits
* to enable interrupt vectors below the given IPL.
*
* Both add and delspl are complicated by the fact that different interrupts
* may share IRQs. This can happen in two ways.
* 1. The same H/W line is shared by more than 1 device
* 1a. with interrupts at different IPLs
* 1b. with interrupts at same IPL
* 2. We ran out of vectors at a given IPL and started sharing vectors.
* 1b and 2 should be handled gracefully, except for the fact some ISRs
* will get called often when no interrupt is pending for the device.
* For 1a, we just hope that the machine blows up with the person who
* set it up that way!. In the meantime, we handle it at the higher IPL.
*/
/*ARGSUSED*/
int
{
int irqindex;
return (PSM_FAILURE);
while (irqptr) {
break;
}
irqptr->airq_share++;
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
/* Or if there are more interupts at a higher IPL */
return (PSM_SUCCESS);
/*
* if apic_picinit() has not been called yet, just return.
* At the end of apic_picinit(), we will call setup_io_intr().
*/
if (!apic_picinit_called)
return (PSM_SUCCESS);
/*
* Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate,
* return failure. Not very elegant, but then we hope the
* machine will blow up with ...
*/
if (vector == 0) {
irqptr->airq_share--;
return (PSM_FAILURE);
}
irqptr = irqheadptr;
while (irqptr) {
/*
* reprogram irq being added and every one else
* who is not in the UNINIT state
*/
iflag = intr_clear();
B_FALSE);
}
}
return (PSM_SUCCESS);
/*
* We cannot upgrade the vector, but we can change
* the IPL that this vector induces.
*
* Note that we subtract APIC_BASE_VECT from the vector
* here because this array is used in apic_intr_enter
* (no need to add APIC_BASE_VECT in that hot code
* path since we can do it in the rarely-executed path
* here).
*/
irqptr = irqheadptr;
while (irqptr) {
}
return (PSM_SUCCESS);
}
iflag = intr_clear();
return (PSM_SUCCESS);
}
/*
* Recompute mask bits for the given interrupt vector.
* If there is no interrupt servicing routine for this
* vector, this function should disable interrupt vector
* from happening at all IPLs. If there are still
* handlers using the given vector, this function should
* disable the given vector from happening below the lowest
* IPL of the remaining hadlers.
*/
/*ARGSUSED*/
int
{
int apic_ix;
while (irqptr) {
break;
}
irqptr->airq_share--;
return (PSM_SUCCESS);
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
if (!apic_picinit_called) {
/*
* Clear irq_struct. If two devices shared an intpt
* line & 1 unloaded before picinit, we are hosed. But, then
* we hope the machine will ...
*/
return (PSM_SUCCESS);
}
/*
* Downgrade vector to new max_ipl if needed.If we cannot allocate,
* use old IPL. Not very elegant, but then we hope ...
*/
irqp = irqheadptr;
while (irqp) {
iflag = intr_clear();
(void) apic_setup_io_intr(irqp,
}
}
}
max_ipl != PSM_INVALID_IPL &&
/*
* We cannot downgrade the IPL of the vector below the vector's
* hardware priority. If we did, it would be possible for a
* higher-priority hardware vector to interrupt a CPU running at an IPL
* lower than the hardware priority of the interrupting vector (but
* higher than the soft IPL of this IRQ). When this happens, we would
* then try to drop the IPL BELOW what it was (effectively dropping
* below base_spl) which would be potentially catastrophic.
*
* (e.g. Suppose the hardware vector associated with this IRQ is 0x40
* (hardware IPL of 4). Further assume that the old IPL of this IRQ
* was 4, but the new IPL is 1. If we forced vector 0x40 to result in
* an IPL of 1, it would be possible for the processor to be executing
* at IPL 3 and for an interrupt to come in on vector 0x40, interrupting
* the currently-executing ISR. When apic_intr_enter consults
* apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1
* so even though the processor was running at IPL 4, an IPL 1
* interrupt will have interrupted it, which must not happen)).
*
* Effectively, this means that the hardware priority corresponding to
* the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's
* hardware priority.
*
* (In the above example, then, after removal of the IPL 4 device's
* interrupt handler, the new IPL will continue to be 4 because the
* hardware priority that IPL 1 implies is lower than the hardware
* priority of the vector used.)
*/
/* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */
/*
* If there are still devices using this IRQ, determine the
* new ipl to use.
*/
if (irqptr->airq_share) {
int vect_desired_hwpri, hwpri;
/*
* If the desired IPL's hardware priority is lower
* than that of the vector, use the hardware priority
* of the vector to determine the new IPL.
*/
/*
* Now, to get the right index for apic_vectortoipl,
* we need to subtract APIC_BASE_VECT from the
* hardware-vector-equivalent (in hwpri). Since hwpri
* is already shifted, we shift APIC_BASE_VECT before
* doing the subtraction.
*/
irqp = irqheadptr;
while (irqp) {
}
} else {
/*
* No more devices on this IRQ, so reset this vector's
* element in apic_ipls to the original IPL for this
* vector
*/
}
}
if (irqptr->airq_share)
return (PSM_SUCCESS);
iflag = intr_clear();
/*
* Disable the MSI vector
* Make sure we only disable on the last
* of the multi-MSI support
*/
}
/*
* Disable the MSI-X vector
*/
/*
* Make sure we only disable on the last MSI-X
*/
}
} else {
/*
* The assumption here is that this is safe, even for
* systems with IOAPICs that suffer from the hardware
* erratum because all devices have been quiesced before
* they unregister their interrupt handlers. If that
* assumption turns out to be false, this mask operation
* can induce the same erratum result we're trying to
* avoid.
*/
}
if (max_ipl == PSM_INVALID_IPL) {
if (bind_cpu & IRQ_USER_BOUND) {
/* If hardbound, temp_cpu == cpu */
bind_cpu &= ~IRQ_USER_BOUND;
} else
}
return (PSM_SUCCESS);
}
/* Move valid irq entry to the head */
while (irqptr) {
break;
}
/* remove all invalid ones from the beginning */
/*
* and link them back after the head. The invalid ones
* begin with irqheadptr and end at oldirqptr
*/
}
return (PSM_SUCCESS);
}
/*
* apic_introp_xlate() replaces apic_translate_irq() and is
* called only from apic_intr_ops(). With the new ADII framework,
* the priority can no longer be retrieved through i_ddi_get_intrspec().
* It has to be passed in from the caller.
*/
int
{
char dev_type[16];
struct apic_io_intr *intrp;
int parent_is_pci_or_pciex = 0;
int child_is_pciex = 0;
irqno));
&dev_len) == DDI_PROP_SUCCESS) {
}
child_is_pciex = 1;
}
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
}
}
bustype = 0;
/* check if we have already translated this irq */
while (airqp) {
}
}
}
if (apic_defconf)
goto defconf;
goto nonpci;
if (parent_is_pci_or_pciex) {
/* pci device */
goto nonpci;
busid = (int)apic_single_pci_busid;
goto nonpci;
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
goto nonpci;
goto nonpci;
return (newirq);
} else {
== NULL) {
goto nonpci;
}
goto nonpci;
return (newirq);
}
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
/* search iso entries first */
if (acpi_iso_cnt != 0) {
i = 0;
while (i < acpi_iso_cnt) {
return (apic_setup_irq_table(
}
i++;
}
}
}
} else {
if (bustype == 0)
for (i = 0; i < 2; i++) {
!= NULL)) {
return (newirq);
}
goto defconf;
}
}
}
/* MPS default configuration */
if (newirq == -1)
return (newirq);
return (newirq);
}
/*
* On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
* needs special handling. We may need to chase up the device tree,
* using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
* to find the IPIN at the root bus that relates to the IPIN on the
* subsidiary bus (for ACPI or MP). We may, however, have an entry
* in the MP table or the ACPI namespace for this device itself.
* We handle both cases in the search below.
*/
/* this is the non-acpi version */
static int
struct apic_io_intr **intrp)
{
int pci_irq;
int bridge_devno, bridge_bus;
int ipin;
/*CONSTCOND*/
while (1) {
return (-1);
PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
NULL) != 0)
return (-1);
/*
* This is the rotating scheme documented in the
* PCI-to-PCI spec. If the PCI-to-PCI bridge is
* behind another PCI-to-PCI bridge, then it needs
* to keep ascending until an interrupt entry is
* found or the root is reached.
*/
bridge_bus = (int)apic_single_pci_busid;
(ipin & 0x3);
bridge_bus)) != NULL) {
return (pci_irq);
}
child_ipin = ipin;
} else {
return (-1);
}
}
/*LINTED: function will not fall off the bottom */
}
static uchar_t
acpi_find_ioapic(int irq)
{
int i;
for (i = 0; i < apic_io_max; i++) {
return (i);
}
return (0xFF); /* shouldn't happen */
}
/*
* See if two irqs are compatible for sharing a vector.
* Currently we only support sharing of PCI devices.
*/
static int
{
/* Assume active high by default */
po1 = 0;
po2 = 0;
return (0);
else
po1 = AV_ACTIVE_LOW;
else
po2 = AV_ACTIVE_LOW;
return (1);
return (0);
}
/*
* Attempt to share vector with someone else
*/
static int
{
#ifdef DEBUG
#endif /* DEBUG */
if (intr_flagp)
newirq = apic_vector_to_irq[i];
if (newirq == APIC_RESV_IRQ)
continue;
/* not compatible */
continue;
chosen_irq = newirq;
}
}
if (chosen_irq != -1) {
/*
* Assign a share id which is free or which is larger
* than the largest one.
*/
share_id = 1;
while (irqptr) {
break;
}
#ifdef DEBUG
#endif /* DEBUG */
}
if (!irqptr) {
#ifdef DEBUG
#endif /* DEBUG */
}
if (intr_flagp)
#ifdef DEBUG
/* shuffle the pointers to test apic_delspl path */
if (tmpirqp) {
}
#endif /* DEBUG */
}
return (-1);
}
/*
*
*/
static int
{
int newirq, intr_index;
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* MSI/X doesn't need to setup ioapic stuffs */
ioapicindex = 0xff;
ioapic = 0xff;
/* need an irq for MSI/X to index into autovect[] */
return (-1);
}
/* Find ioapicindex. If destid was ALL, we will exit with 0. */
break;
(ioapic == INTR_ALL_APIC));
/* check whether this intin# has been used by another irqno */
return (newirq);
}
} else if (intr_flagp != NULL) {
/* ACPI case */
if (apic_irq_table[irqno] &&
return (irqno);
}
} else {
/* default configuration */
ioapicindex = 0;
}
irqno));
/* This is OK to do really */
" instance %d and SCI",
} else {
" instance %d and %s instance %d",
}
return (newirq);
}
/* try high priority allocation now that share has failed */
return (-1);
}
}
} else {
/*
* The slot is used by another irqno, so allocate
* a free irqno for this interrupt
*/
if (newirq == -1) {
return (-1);
}
KM_SLEEP);
}
}
}
irqptr->airq_share_id = 0;
if (intr_flagp)
if (!DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* setup I/O APIC entry for non-MSI/X interrupts */
}
return (irqno);
}
/*
* return the cpu to which this intr should be bound.
* Check properties or any other mechanism to see if user wants it
* bound to a specific CPU. If so, return the cpu id with high bit set.
* If not, use the policy to choose a cpu and return the id.
*/
{
char prop_name[32];
if (apic_intr_policy == INTR_LOWEST_PRIORITY)
return (IRQ_UNBOUND);
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
== FREE_INDEX))
continue;
(!(apic_irq_table[i]->airq_cpu &
IRQ_USER_BOUND))) {
"!%s: %s (%s) instance #%d "
"vector 0x%x ioapic 0x%x "
"intin 0x%x is bound to cpu %d\n",
return (cpu);
}
}
}
/*
* search for "drvname"_intpt_bind_cpus property first, the
* syntax of the property should be "a[,b,c,...]" where
* instance 0 binds to cpu a, instance 1 binds to cpu b,
* instance 3 binds to cpu c...
* ddi_getlongprop() will search /option first, then /
* if "drvname"_intpt_bind_cpus doesn't exist, then find
* intpt_bind_cpus property. The syntax is the same, and
* it applies to all the devices if its "drvname" specific
* property doesn't exist
*/
if (rc != DDI_PROP_SUCCESS) {
}
}
if (rc == DDI_PROP_SUCCESS) {
if (prop_val[i] == ',')
count++;
count++;
/*
* if somehow the binding instances defined in the
* property are not enough for this instno., then
* reuse the pattern for the next instance until
* it reaches the requested instno
*/
i = 0;
while (i < instno)
if (*cptr++ == ',')
i++;
/* if specific cpu is bogus, then default to cpu 0 */
if (bind_cpu >= apic_nproc) {
bind_cpu = 0;
} else {
/* indicate that we are bound at user request */
}
/*
* no need to check apic_cpus[].aci_status, if specific cpu is
* not up, then post_cpu_start will handle it.
*/
} else {
if (bind_cpu >= apic_nproc) {
apic_next_bind_cpu = 1;
bind_cpu = 0;
}
}
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
else
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
}
static struct apic_io_intr *
{
struct apic_io_intr *intrp;
/*
* It can have more than 1 entry with same source bus IRQ,
* but unique with the source bus id
*/
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
struct mps_bus_info {
char *bus_name;
int bus_id;
} bus_info_array[] = {
"ISA ", BUS_ISA,
"PCI ", BUS_PCI,
"EISA ", BUS_EISA,
"XPRESS", BUS_XPRESS,
"PCMCIA", BUS_PCMCIA,
"VL ", BUS_VL,
"CBUS ", BUS_CBUS,
"CBUSII", BUS_CBUSII,
"FUTURE", BUS_FUTURE,
"INTERN", BUS_INTERN,
"MBI ", BUS_MBI,
"MBII ", BUS_MBII,
"MPI ", BUS_MPI,
"MPSA ", BUS_MPSA,
"NUBUS ", BUS_NUBUS,
"TC ", BUS_TC,
"VME ", BUS_VME,
"PCI-E ", BUS_PCIE
};
static int
apic_find_bus_type(char *bus)
{
int i = 0;
for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
return (bus_info_array[i].bus_id);
return (0);
}
static int
apic_find_bus(int busid)
{
busp++;
}
return (0);
}
static int
apic_find_bus_id(int bustype)
{
busp++;
}
bustype));
return (-1);
}
/*
* Check if a particular irq need to be reserved for any io_intr
*/
static struct apic_io_intr *
apic_find_io_intr(int irqno)
{
struct apic_io_intr *intrp;
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
/*
* Check if the given ioapicindex intin combination has already been assigned
* an irq. If so return irqno. Else -1
*/
static int
{
int i;
/* find ioapic and intin in the apic_irq_table[] and return the index */
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
irqptr = apic_irq_table[i];
while (irqptr) {
if ((irqptr->airq_mps_intr_index >= 0) &&
"entry for ioapic:intin %x:%x "
return (i);
}
}
}
return (-1);
}
int
apic_allocate_irq(int irq)
{
int freeirq, i;
/*
* if BIOS really defines every single irq in the mps
* table, then don't worry about conflicting with
* them, just use any free slot in apic_irq_table
*/
for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
if ((apic_irq_table[i] == NULL) ||
FREE_INDEX) {
freeirq = i;
break;
}
}
if (freeirq == -1) {
/* This shouldn't happen, but just in case */
return (-1);
}
}
psm_name);
return (-1);
}
}
return (freeirq);
}
static int
{
int i;
/* Check if any I/O entry needs this IRQ */
if (apic_find_io_intr(i) == NULL) {
/* Then see if it is free */
if ((apic_irq_table[i] == NULL) ||
(apic_irq_table[i]->airq_mps_intr_index ==
FREE_INDEX)) {
return (i);
}
}
return (-1);
}
/*
* Mark vector as being in the process of being deleted. Interrupts
* may still come in on some CPU. The moment an interrupt comes with
* the new vector, we know we can free the old one. Called only from
* addspl and delspl with interrupts disabled. Because an interrupt
* can be shared, but no interrupt from either device may come in,
* we also use a timeout mechanism, which we arbitrarily set to
* apic_revector_timeout microseconds.
*/
static void
{
iflag = intr_clear();
if (!apic_oldvec_to_newvec) {
if (!apic_oldvec_to_newvec) {
/*
* This failure is not catastrophic.
* But, the oldvec will never be freed.
*/
return;
}
}
/* See if we already did this for drivers which do double addintrs */
}
}
/*
* xlate_vector is called from intr_enter if revector_pending is set.
* It will xlate it if needed and mark the old vector as free.
*/
{
/* Do we really need to do this ? */
if (!apic_revector_pending) {
return (vector);
}
else {
/*
* The incoming vector is new . See if a stale entry is
* remaining
*/
}
if (oldvector) {
/* There could have been more than one reprogramming! */
return (apic_xlate_vector(newvector));
}
return (vector);
}
void
{
iflag = intr_clear();
}
}
/*
* compute the polarity, trigger mode and vector for programming into
* the I/O apic and record in airq_rdt_entry.
*/
static void
{
short intr_index;
struct apic_io_intr *iointrp;
if (intr_index == RESERVE_INDEX) {
return;
} else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
return;
}
/* Assume edge triggered by default */
level = 0;
/* Assume active high by default */
po = 0;
} else if (intr_index == ACPI_INDEX) {
} else
AV_LEVEL : 0;
if (level &&
po = AV_ACTIVE_LOW;
} else {
} else
AV_LEVEL : 0;
po = AV_ACTIVE_LOW;
}
if (level)
/*
* The 82489DX External APIC cannot do active low polarity interrupts.
*/
else
io_po = 0;
printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n",
}
/*
* Bind interrupt corresponding to irq_ptr to bind_cpu.
* Must be called with interrupts disabled and apic_ioapic_lock held
*/
int
struct ioapic_reprogram_data *drep)
{
int ioapicindex, intin_no;
int which_irq;
if (airq_temp_cpu & IRQ_USER_BOUND)
/* Mask off high bit so it can be used as array index */
}
/*
* Can't bind to a CPU that's not accepting interrupts:
*/
return (1);
/*
* If we are about to change the interrupt vector for this interrupt,
* and this interrupt is level-triggered, attached to an IOAPIC,
* has been delivered to a CPU and that CPU has not handled it
* yet, we cannot reprogram the IOAPIC now.
*/
intin_no);
return (0);
}
/*
* NOTE: We do not unmask the RDT here, as an interrupt MAY
* still come in before we have a chance to reprogram it below.
* The reprogramming below will simultaneously change and
* unmask the RDT entry.
*/
/* Write the RDT entry -- no specific CPU binding */
AV_TOALL);
/*
* Write the vector, trigger, and polarity portion of
* the RDT
*/
return (0);
}
}
if (bind_cpu & IRQ_USER_BOUND) {
} else {
}
/* Write the RDT entry -- bind to a specific CPU: */
}
}
/* Write the vector, trigger, and polarity portion of the RDT */
} else {
if (type == DDI_INTR_TYPE_MSI) {
if (irq_ptr->airq_ioapicindex ==
irq_ptr->airq_origirq) {
/* first one */
"apic_pci_msi_enable_vector\n"));
}
if ((irq_ptr->airq_ioapicindex +
"apic_pci_msi_enable_mode\n"));
}
} else { /* MSI-X */
}
}
return (0);
}
static void
{
& AV_REMOTE_IRR) != 0) {
/*
* Trying to clear the bit through normal
* channels has failed. So as a last-ditch
* effort, try to set the trigger mode to
* edge, then to level. This has been
* observed to work on many systems.
*/
/*
* If the bit's STILL set, this interrupt may
* be hosed.
*/
intin_no) & AV_REMOTE_IRR) != 0) {
prom_printf("%s: Remote IRR still "
"not clear for IOAPIC %d intin %d.\n"
"\tInterrupts to this pin may cease "
intin_no);
#ifdef DEBUG
#endif
}
}
}
/*
* This function is protected by apic_ioapic_lock coupled with the
* fact that interrupts are disabled.
*/
static void
{
return;
#ifdef DEBUG
#endif
if (--apic_reprogram_outstanding == 0) {
setlvlx = psm_intr_exit_fn();
}
}
/*
* Interrupts must be disabled during this function to prevent
* self-deadlock. Interrupts are disabled because this function
* is called from apic_check_stuck_interrupt(), which is called
* from apic_rebind(), which requires its caller to disable interrupts.
*/
static void
{
/*
* On the off-chance that there's already a deferred
* reprogramming on this irq, check, and if so, just update the
* CPU and irq pointer to which the interrupt is targeted, then return.
*/
return;
}
/*
* This must be the last thing set, since we're not
* grabbing any locks, apic_try_deferred_reprogram() will
* make its decision about using this entry iff done
* is false.
*/
/*
* If there were previously no deferred reprogrammings, change
* setlvlx to call apic_try_deferred_reprogram()
*/
if (++apic_reprogram_outstanding == 1) {
}
}
static void
{
struct ioapic_reprogram_data *drep;
if (!lock_try(&apic_defer_reprogram_lock)) {
return;
}
/*
* Acquire the apic_ioapic_lock so that any other operations that
* may affect the apic_reprogram_info state are serialized.
* It's still possible for the last deferred reprogramming to clear
* between the time we entered this function and the time we get to
* the for loop below. In that case, *setlvlx will have been set
* back to *_intr_exit and drep will be NULL. (There's no way to
* stop that from happening -- we would need to grab a lock before
* calling *setlvlx, which is neither realistic nor prudent).
*/
iflag = intr_clear();
/*
* For each deferred RDT entry, try to reprogram it now. Note that
* there is no lock acquisition to read apic_reprogram_info because
* '.done' is set only after the other fields in the structure are set.
*/
break;
}
}
/*
* Either we found a deferred action to perform, or
* we entered this function spuriously, after *setlvlx
* was restored to point to *_intr_exit. Any other
* permutation is invalid.
*/
/*
* Though we can't really do anything about errors
* at this point, keep track of them for reporting.
* Note that it is very possible for apic_setup_io_intr
* to re-register this very timeout if the Remote IRR bit
* has not yet cleared.
*/
#ifdef DEBUG
}
} else {
}
#else
#endif
}
static void
{
int waited;
/*
* Wait for the delivery pending bit to clear.
*/
/*
* If we're still waiting on the delivery of this interrupt,
* continue to wait here until it is delivered (this should be
* a very small amount of time, but include a timeout just in
* case).
*/
waited++) {
intin_no) & AV_PENDING) == 0) {
break;
}
}
}
}
/*
* Checks to see if the IOAPIC interrupt entry specified has its Remote IRR
* bit set. Calls functions that modify the function that setlvlx points to,
* so that the reprogramming can be retried very shortly.
*
* This function will mask the RDT entry if the interrupt is level-triggered.
* (The caller is responsible for unmasking the RDT entry.)
*
* Returns non-zero if the caller should defer IOAPIC reprogramming.
*/
static int
struct ioapic_reprogram_data *drep)
{
int waited;
int reps = 0;
/*
* Wait for the delivery pending bit to clear.
*/
do {
++reps;
/*
* Mask the RDT entry, but only if it's a level-triggered
* interrupt
*/
intin_no);
/* Mask it */
}
/*
* If there was a race and an interrupt was injected
* just before we masked, check for that case here.
* Then, unmask the RDT entry and try again. If we're
* on our last try, don't unmask (because we want the
* RDT entry to remain masked for the rest of the
* function).
*/
intin_no);
if ((rdt_entry & AV_PENDING) &&
(reps < apic_max_reps_clear_pending)) {
/* Unmask it */
}
}
} while ((rdt_entry & AV_PENDING) &&
#ifdef DEBUG
if (rdt_entry & AV_PENDING)
#endif
/*
* If the remote IRR bit is set, then the interrupt has been sent
* to a CPU for processing. We have no choice but to wait for
* that CPU to process the interrupt, at which point the remote IRR
* bit will be cleared.
*/
/*
* If the CPU that this RDT is bound to is NOT the current
* CPU, wait until that CPU handles the interrupt and ACKs
* it. If this interrupt is not bound to any CPU (that is,
* if it's bound to the logical destination of "anyone"), it
* may have been delivered to the current CPU so handle that
* case by deferring the reprogramming (below).
*/
if ((old_bind_cpu != IRQ_UNBOUND) &&
(old_bind_cpu != IRQ_UNINIT) &&
(old_bind_cpu != psm_get_cpu_id())) {
waited++) {
intin_no) & AV_REMOTE_IRR) == 0) {
/* Remote IRR has cleared! */
return (0);
}
}
}
/*
* If we waited and the Remote IRR bit is still not cleared,
* AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
* times for this interrupt, try the last-ditch workaround:
*/
/* Mark this one as reprogrammed: */
return (0);
} else {
#ifdef DEBUG
#endif
/*
* If waiting for the Remote IRR bit (above) didn't
* allow it to clear, defer the reprogramming.
* Add a new deferred-programming entry if the
* caller passed a NULL one (and update the existing one
* in case anything changed).
*/
if (drep)
/* Inform caller to defer IOAPIC programming: */
return (1);
}
}
/* Remote IRR is clear */
return (0);
}
/*
* Called to migrate all interrupts at an irq to another cpu.
* Must be called with interrupts disabled and apic_ioapic_lock held
*/
int
{
int retval = 0;
while (irqptr) {
}
return (retval);
}
/*
* apic_intr_redistribute does all the messy computations for identifying
* which interrupt to move to which CPU. Currently we do just one interrupt
* at a time. This reduces the time we spent doing all this within clock
* interrupt. When it is done in idle, we could do more than 1.
* First we find the most busy and the most free CPU (time in ISR only)
* skipping those CPUs that has been identified as being ineligible (cpu_skip)
* Then we look for IRQs which are closest to the difference between the
* most busy CPU and the average ISR load. We try to find one whose load
* is less than difference.If none exists, then we chose one larger than the
* difference, provided it does not make the most idle CPU worse than the
* most busy one. In the end, we clear all the busy fields for CPUs. For
* IRQs, they are cleared as they are scanned.
*/
void
{
int busiest_cpu, most_free_cpu;
int average_busy, cpus_online;
cpus_online = 0;
/*
* Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu
* without ioapic_lock. That is OK as we are just doing statistical
* sampling anyway and any inaccuracy now will get corrected next time
* The call to rebind which actually changes things will make sure
* we are consistent.
*/
for (i = 0; i < apic_nproc; i++) {
if (!(apic_redist_cpu_skip & (1 << i)) &&
/*
* If no unbound interrupts or only 1 total on this
* CPU, skip
*/
if (!cpu_infop->aci_temp_bound ||
== 1) {
apic_redist_cpu_skip |= 1 << i;
continue;
}
average_busy += busy;
cpus_online++;
busiest_cpu = i;
}
most_free_cpu = i;
}
if (busy > apic_int_busy_mark) {
cpu_busy |= 1 << i;
} else {
if (busy < apic_int_free_mark)
cpu_free |= 1 << i;
}
}
}
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
"redistribute busy=%x free=%x max=%x min=%x",
}
#endif /* DEBUG */
max_busy = 0;
i = apic_min_device_irq;
for (; i < apic_max_device_irq; i++) {
/* Change to linked list per CPU ? */
continue;
/* Check for irq_busy & decide which one to move */
/* Also zero them for next round */
/*
* Check for least busy CPU,
* best fit or what ?
*/
/*
* Most busy within the
* required differential
*/
}
} else {
/*
* least busy, but more than
* the reqd diff
*/
if (min_busy <
(diff + average_busy -
min_free)) {
/*
* Making sure new cpu
* will not end up
* worse
*/
min_busy =
}
}
}
}
}
if (max_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
iflag = intr_clear();
if (lock_try(&apic_ioapic_lock)) {
most_free_cpu) == 0) {
/* Make change permenant */
}
}
} else if (min_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
iflag = intr_clear();
if (lock_try(&apic_ioapic_lock)) {
most_free_cpu) == 0) {
/* Make change permenant */
}
}
} else {
/*
* We leave cpu_skip set so that next time we
* can choose another cpu
*/
}
}
} else {
/*
* found nothing. Could be that we skipped over valid CPUs
* or we have balanced everything. If we had a variable
* ticks_for_redistribution, it could be increased here.
* apic_int_busy, int_free etc would also need to be
* changed.
*/
if (apic_redist_cpu_skip)
apic_redist_cpu_skip = 0;
}
for (i = 0; i < apic_nproc; i++) {
}
}
void
{
int i;
for (i = 0; i < apic_nproc; i++) {
}
for (i = apic_min_device_irq; i < apic_max_device_irq; i++) {
}
}
static int
{
int status;
intr_flagp)) == ACPI_PSM_SUCCESS) {
"from cache for device %s, instance #%d\n", psm_name,
return (status);
}
&acpipsmlnk)) == ACPI_PSM_FAILURE) {
" acpi_translate_pci_irq failed for device %s, instance"
ddi_get_instance(dip)));
return (status);
}
if (status != ACPI_PSM_SUCCESS) {
}
}
if (status == ACPI_PSM_SUCCESS) {
intr_flagp, &acpipsmlnk);
"new irq %d for device %s, instance #%d\n", psm_name,
}
return (status);
}
/*
* Adds an entry to the irq list passed in, and returns the new list.
* Entries are added in priority order (lower numerical priorities are
* placed closer to the head of the list)
*/
static prs_irq_list_t *
{
/* ->next is NULL from kmem_zalloc */
/*
* New list -- return the new entry as the list.
*/
return (newent);
/*
* Save original list pointer for return (since we're not modifying
* the head)
*/
/*
* Insertion sort, with entries with identical keys stored AFTER
* existing entries (the less-than-or-equal test of priority does
* this for us).
*/
}
return (newent);
} else {
return (origlistp);
}
}
/*
* Frees the list passed in, deallocating all memory and leaving *listpp
* set to NULL.
*/
static void
{
struct prs_irq_list_ent *nextp;
}
}
/*
* apic_choose_irqs_from_prs returns a list of irqs selected from the list of
* irqs returned by the link device's _PRS method. The irqs are chosen
* to minimize contention in situations where the interrupt link device
* can be programmed to steer interrupts to different interrupt controller
* inputs (some of which may already be in use). The list is sorted in order
* of irqs to use, with the highest priority given to interrupt controller
* inputs that are not shared. When an interrupt controller input
* must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
* returned list in the order that minimizes sharing (thereby ensuring lowest
* possible latency from interrupt trigger time to ISR execution time).
*/
static prs_irq_list_t *
int crs_irq)
{
int i;
while (irqlistent != NULL) {
for (i = 0; i < irqlistent->num_irqs; i++) {
if (irq <= 0) {
/* invalid irq number */
continue;
}
continue;
/*
* If we do not prefer the current irq from _CRS
* or if we do and this irq is the same as the
* current irq from _CRS, this is the one
* to pick.
*/
return (prsirqlistp);
}
continue;
}
/*
* Edge-triggered interrupts cannot be shared
*/
continue;
/*
* To work around BIOSes that contain incorrect
* interrupt polarity information in interrupt
* descriptors returned by _PRS, we assume that
* the polarity of the other device sharing this
* interrupt controller input is compatible.
* If it's not, the caller will catch it when
* the caller invokes the link device's _CRS method
* (after invoking its _SRS method).
*/
if (!acpi_intr_compatible(iflags,
"not compatible [%x:%x:%x !~ %x:%x:%x]",
continue;
}
/*
* If we prefer the irq from _CRS, no need
* to search any further (and make sure
* to add this irq with the highest priority
* so it's tried first).
*/
return (acpi_insert_prs_irq_ent(
0 /* Highest priority */,
&irqlistent->acpi_prs_prv));
}
/*
* Priority is equal to the share count (lower
* share count is higher priority). Note that
* the intr flags passed in here are the ones we
* changed above -- if incorrect, it will be
* caught by the caller's _CRS flags comparison.
*/
}
/* Go to the next irqlist entry */
}
return (prsirqlistp);
}
/*
* Configures the irq for the interrupt link device identified by
* acpipsmlnkp.
*
* Gets the current and the list of possible irq settings for the
* device. If apic_unconditional_srs is not set, and the current
* resource setting is in the list of possible irq settings,
* current irq resource setting is passed to the caller.
*
* Otherwise, picks an irq number from the list of possible irq
* settings, and sets the irq of the device to this value.
* If prefer_crs is set, among a set of irq numbers in the list that have
* the least number of devices sharing the interrupt, we pick current irq
* resource setting if it is a member of this set.
*
* Passes the irq number in the value pointed to by pci_irqp, and
* polarity and sensitivity in the structure pointed to by dipintrflagp
* to the caller.
*
* Note that if setting the irq resource failed, but successfuly obtained
* the current irq resource settings, passes the current irq resources
* and considers it a success.
*
* Returns:
* ACPI_PSM_SUCCESS on success.
*
* ACPI_PSM_FAILURE if an error occured during the configuration or
* if a suitable irq was not found for this device, or if setting the
* irq resource and obtaining the current resource fails.
*
*/
static int
{
int cur_irq = -1;
== ACPI_PSM_FAILURE) {
"or assign IRQ for device %s, instance #%d: The system was "
"unable to get the list of potential IRQs from ACPI.",
return (ACPI_PSM_FAILURE);
}
(cur_irq > 0)) {
/*
* If an IRQ is set in CRS and that IRQ exists in the set
* returned from _PRS, return that IRQ, otherwise print
* a warning
*/
== ACPI_PSM_SUCCESS) {
return (ACPI_PSM_SUCCESS);
}
"current irq %d for device %s, instance #%d in ACPI's "
"list of possible irqs for this device. Picking one from "
ddi_get_instance(dip)));
}
"suitable irq from the list of possible irqs for device "
"%s, instance #%d in ACPI's list of possible irqs",
return (ACPI_PSM_FAILURE);
}
for (prs_irq_entp = prs_irq_listp;
== ACPI_PSM_SUCCESS) {
/*
* setting irq was successful, check to make sure CRS
* reflects that. If CRS does not agree with what we
* set, return the irq that was set.
*/
dipintr_flagp) == ACPI_PSM_SUCCESS) {
"!%s: IRQ resource set "
"(irqno %d) for device %s "
"instance #%d, differs from "
"current setting irqno %d",
} else {
/*
* On at least one system, there was a bug in
* a DSDT method called by _STA, causing _STA to
* indicate that the link device was disabled
* (when, in fact, it was enabled). Since _SRS
* succeeded, assume that _CRS is lying and use
* the iflags from this _PRS interrupt choice.
* If we're wrong about the flags, the polarity
* will be incorrect and we may get an interrupt
* storm, but there's not much else we can do
* at this point.
*/
}
/*
* Return the irq that was set, and not what _CRS
* reports, since _CRS has been seen to return
* different IRQs than what was passed to _SRS on some
* systems (and just not return successfully on others).
*/
} else {
"irq %d failed for device %s instance #%d",
ddi_get_instance(dip)));
if (cur_irq == -1) {
return (ACPI_PSM_FAILURE);
}
}
}
if (!found_irq)
return (ACPI_PSM_FAILURE);
return (ACPI_PSM_SUCCESS);
}
void
{
int ioapic_ix;
int intin_max;
int intin_ix;
/* Disable the I/O APIC redirection entries */
/* Bits 23-16 define the maximum redirection entries */
& 0xff;
/*
* The assumption here is that this is safe, even for
* systems with IOAPICs that suffer from the hardware
* erratum because all devices have been quiesced before
* this function is called from apic_shutdown()
* (or equivalent). If that assumption turns out to be
* false, this mask operation can induce the same
* erratum result we're trying to avoid.
*/
AV_MASK);
}
}
}
/*
* Looks for an IOAPIC with the specified physical address in the /ioapics
* node in the device tree (created by the PCI enumerator).
*/
static boolean_t
{
/*
* Look in /ioapics, for the ioapic with
* the physical address given
*/
if (ioapicsnode == NULL)
return (B_FALSE);
/* Load first child: */
!= 0 && physaddr == ioapic_paddr) {
IOAPICS_PROP_DEVID, 0);
if (did == DEVID_8131_IOAPIC ||
did == DEVID_8132_IOAPIC) {
}
}
}
if (!done)
}
/* The ioapics node was held by ddi_find_devinfo, so release it */
return (rv);
}
struct apic_state {
};
static void
{
int i;
/*
* First the local APIC.
*/
/*
* if on the boot processor then save the IO APICs.
*/
if (psm_get_cpu_id() == 0) {
for (i = 0; i < apic_io_max; i++) {
int intin_max, j;
/* Bits 23-16 define the maximum redirection entries */
#if 0 /* debug */
prom_printf("\nIOAPIC %d (%d redirs):\n",
i, intin_max+1);
#endif /* debug */
for (j = 0; j <= intin_max; j++) {
#if 0 /* debug */
#endif /* debug */
}
}
}
}
static void
{
int i;
int iflag;
int rv;
int retval = 0;
/*
* First the local APIC.
*/
/*
* the following only needs to be done once, so we do it on the
* boot processor, since we know that we only have one of those
*/
if (psm_get_cpu_id() == 0) {
/*
* regenerate the IO APICs.
*/
iflag = intr_clear();
for (i = apic_min_device_irq; i < apic_max_device_irq; i++) {
continue;
continue;
B_FALSE);
if (rv) {
("apic_setup_io_intr(%p, "
"%d) %d\n", (void *)irqp,
i, rv));
}
}
}
}
/*
* restore acpi link device mappings
*/
}
}
/*
* Returns 0 on success
*/
int
{
case PSM_STATE_ALLOC:
return (ENOMEM);
sizeof (struct apic_state);
return (0);
case PSM_STATE_FREE:
return (0);
case PSM_STATE_SAVE:
return (0);
case PSM_STATE_RESTORE:
return (0);
default:
return (EINVAL);
}
}