/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2016 Nexenta Systems, Inc.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
* PSMI 1.6 extensions are supported in Solaris Nevada.
* PSMI 1.7 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_7
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include <sys/apic_timer.h>
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
#if !defined(__xpv)
#endif
/*
* Local Function Prototypes
*/
static int apic_handle_defconf();
static int apic_find_bus_type(char *bus);
static int apic_find_bus(int busid);
static void apic_free_apic_cpus(void);
static int apic_acpi_enter_apicmode(void);
int apic_find_bus_id(int bustype);
/* ACPI SCI interrupt configuration; -1 if SCI not used */
#if !defined(__xpv)
/* ACPI HPET interrupt configuration; -1 if HPET not used */
#endif
/*
* psm name pointer
*/
char *psm_name;
/* ACPI support routines */
static int acpi_probe(char *);
/* Max wait time (in repetitions) for flags to clear in an RDT entry. */
/* start with cpu 1 */
/*
* If enabled, the distribution works as follows:
* On every interrupt entry, the current ipl for the CPU is set in cpu_info
* and the irq corresponding to the ipl is also set in the aci_current array.
* interrupt exit and setspl (due to soft interrupts) will cause the current
* ipl to be be changed. This is cache friendly as these frequently used
* paths write into a per cpu structure.
*
* Sampling is done by checking the structures for all CPUs and incrementing
* the busy field of the irq (if any) executing on each CPU and the busy field
* of the corresponding CPU.
* In periodic mode this is done on every clock interrupt.
* In one-shot mode, this is done thru a cyclic with an interval of
* apic_redistribute_sample_interval (default 10 milli sec).
*
* Every apic_sample_factor_redistribution times we sample, we do computations
* to decide which interrupt needs to be migrated (see comments
* before apic_intr_redistribute().
*/
/*
* Following 3 variables start as % and can be patched or set using an
* API to be defined in future. They will be scaled to
* sample_factor_redistribution which is in turn set to hertz+1 (in periodic
* mode), or 101 in one-shot mode to stagger it away from one sec processing
*/
/* sampling interval for interrupt redistribution for dynamic migration */
/*
* number of times we sample before deciding to redistribute interrupts
* for dynamic migration
*/
int apic_redist_cpu_skip = 0;
int apic_num_imbalance = 0;
int apic_num_rebind = 0;
/*
* Maximum number of APIC CPUs in the system, -1 indicates that dynamic
* allocation of CPU ids is disabled.
*/
int apic_nproc = 0;
int apic_defconf = 0;
int apic_irq_translate = 0;
int apic_spec_rev = 0;
int apic_imcrp = 0;
/*
* For interrupt link devices, if apic_unconditional_srs is set, an irq resource
* will be assigned (via _SRS). If it is not set, use the current
* irq setting (via _CRS), but only if that irq is in the set of possible
* irqs (returned by _PRS) for the device.
*/
/*
* For interrupt link devices, if apic_prefer_crs is set when we are
* assigning an IRQ resource to a device, prefer the current IRQ setting
* over other possible irq settings under same conditions.
*/
/*
* First available slot to be used as IRQ index into the apic_irq_table
* for those interrupts (like MSI/X) that don't have a physical IRQ.
*/
/*
* apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
* and bound elements of cpus_info and the temp_cpu element of irq_struct
*/
/* At least MSB will be set if EISA bus */
int apic_pci_bus_total = 0;
/*
* airq_mutex protects additions to the apic_irq_table - the first
* pointer and any airq_nexts off of that one. It also protects
* apic_max_device_irq & apic_min_device_irq. It also guarantees
* that share_id is unique as new ids are generated only when new
* irq_t structs are linked in. Once linked in the structs are never
* deleted. temp_cpu & mps_intr_index field indicate if it is programmed
* or allocated. Note that there is a slight gap between allocating in
* apic_introp_xlate and programming in addspl.
*/
int apic_max_device_irq = 0;
typedef struct prs_irq_list_ent {
int list_prio;
/*
* ACPI variables
*/
/* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
int apic_enable_acpi = 0;
/* ACPI Multiple APIC Description Table ptr */
/* ACPI Interrupt Source Override Structure ptr */
int acpi_iso_cnt = 0;
/* ACPI Non-maskable Interrupt Sources ptr */
static int acpi_nmi_scnt = 0;
static int acpi_nmi_ccnt = 0;
/*
* The following added to identify a software poweroff method if available.
*/
static struct {
int poweroff_method;
} apic_mps_ids[] = {
};
/*
* Auto-configuration routines
*/
/*
* Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
* May work with 1.1 - but not guaranteed.
* According to the MP Spec, the MP floating pointer structure
* will be searched in the order described below:
* 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
* 2. Within the last kilobyte of system base memory
* 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
* Once we find the right signature with proper checksum, we call
* either handle_defconf or parse_mpct to get all info necessary for
* subsequent operations.
*/
int
{
int acpi_user_options;
if (apic_forceload < 0)
return (retval);
/*
* Remember who we are
*/
/* Allow override for MADT-only mode */
"acpi-user-options", 0);
/* Allow apic_use_acpi to override MADT-only mode */
if (!apic_use_acpi)
/*
* mapin the bios data area 40:0
* 40:13h - two-byte location reports the base memory size
* 40:0Eh - two-byte location for the exact starting address of
* the EBDA segment for EISA
*/
if (!biosdatap)
goto apic_ret;
/*LINTED: pointer cast may result in improper alignment */
/* check the 1k of EBDA */
if (ebda_seg) {
if (fptr) {
if (!(fpsp =
}
}
/* If not in EBDA, check the last k of system base memory */
if (!fpsp) {
/*LINTED: pointer cast may result in improper alignment */
if (base_mem_size > 512)
else
/* if ebda == last k of base mem, skip to check BIOS ROM */
if (base_mem_end != ebda_start) {
if (fptr) {
}
}
}
/* If still cannot find it, check the BIOS ROM space */
if (!fpsp) {
if (fptr) {
if (!(fpsp =
goto apic_ret;
}
}
}
goto apic_ret;
}
goto apic_ret;
}
/* check IMCR is present or not */
/* check default configuration (dual CPUs) */
return (retval);
goto apic_ret;
}
/* MP Configuration Table */
/*
* Map in enough memory for the MP Configuration Table Header.
* Use this table to read the total length of the BIOS data and
* map in all the info
*/
/*LINTED: pointer cast may result in improper alignment */
sizeof (struct apic_mp_cnf_hdr), PROT_READ);
if (!hdrp)
goto apic_ret;
/* check mp configuration table signature PCMP */
goto apic_ret;
}
/* This is an ACPI machine No need for further checks */
goto apic_ret;
}
/*
* Map in the entries for this machine, ie. Processor
* Entry Tables, Bus Entry Tables, etc.
* They are in fixed order following one another
*/
if (!mpct)
goto apic_ret;
goto apic_fail1;
/*LINTED: pointer cast may result in improper alignment */
if (!apicadr)
goto apic_fail1;
/* Parse all information in the tables */
PSM_SUCCESS) {
goto apic_ret;
}
if (retval == PSM_SUCCESS) {
extern int apic_ioapic_method_probe();
return (PSM_SUCCESS);
}
for (i = 0; i < apic_io_max; i++)
if (apic_cpus) {
}
if (apicadr) {
}
if (mpct)
return (retval);
}
static void
{
int i;
for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
i++) {
break;
}
}
if (apic_debug_mps_id != 0) {
"Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
hdrp->mpcnf_oem_str[0],
hdrp->mpcnf_prod_str[0],
}
}
static void
apic_free_apic_cpus(void)
{
apic_cpus_size = 0;
}
}
static int
{
int acpi_verboseflags = 0;
int sci;
int ioapic_ix;
int warned = 0;
if (!apic_use_acpi)
return (PSM_FAILURE);
return (PSM_FAILURE);
if (!apicadr)
return (PSM_FAILURE);
KM_NOSLEEP)) == NULL)
return (PSM_FAILURE);
KM_NOSLEEP)) == NULL) {
return (PSM_FAILURE);
}
apic_io_max = 0;
madt_seen = sizeof (*acpi_mapic_dtp);
"invalid entry in MADT: CPU %d "
"has Local APIC Id equal to 255 ",
}
apic_nproc < boot_ncpus) {
index++;
apic_nproc++;
"exceeded"
#if !defined(__amd64)
" for 32-bit mode"
#endif
"; Solaris will use %d CPUs.",
warned = 1;
}
}
break;
case ACPI_MADT_TYPE_IO_APIC:
if (apic_io_max < MAX_IO_APIC) {
if (!ioapic)
goto cleanup;
apic_io_max++;
}
break;
acpi_iso_cnt++;
break;
/* UNIMPLEMENTED */
if (acpi_nmi_sp == NULL)
acpi_nmi_sp = mns;
break;
/* UNIMPLEMENTED */
if (acpi_nmi_cp == NULL)
acpi_nmi_cp = mlan;
break;
/* UNIMPLEMENTED */
break;
case ACPI_MADT_TYPE_IO_SAPIC:
/* UNIMPLEMENTED */
break;
/* UNIMPLEMENTED */
"!apic: irq source: %d %d %d 0x%x %d %d\n",
mis->IoSapicVector);
break;
/*
* All logical processors with APIC ID values
* of 255 and greater will have their APIC
* reported through Processor X2APIC structure.
* All logical processors with APIC ID less than
* 255 will have their APIC reported through
* Processor Local APIC.
*
* Some systems apparently don't care and report all
* processors through Processor X2APIC structures. We
* warn about that but don't ignore those CPUs.
*/
"in MADT: CPU %d has X2APIC Id %d (< 255)",
}
apic_nproc < boot_ncpus) {
index++;
apic_nproc++;
"exceeded"
#if !defined(__amd64)
" for 32-bit mode"
#endif
"; Solaris will use %d CPUs.",
warned = 1;
}
}
break;
/* UNIMPLEMENTED */
#ifdef DEBUG
"!apic: local x2apic nmi: %d 0x%x %d\n",
#endif
break;
case ACPI_MADT_TYPE_RESERVED:
default:
break;
}
/* advance to next entry */
}
/*
* allocate enough space for possible hot-adding of CPUs.
* max_ncpus may be less than apic_nproc if it's set by user.
*/
if (plat_dr_support_cpu()) {
}
goto cleanup;
/*
* ACPI doesn't provide the local apic ver, get it directly from the
* local apic
*/
for (i = 0; i < apic_nproc; i++) {
/* Only build mapping info for CPUs present at boot. */
if (i < boot_ncpus)
(void) acpica_map_cpu(i, proc_ids[i]);
}
/*
* To support CPU dynamic reconfiguration, the apic CPU info structure
* for each possible CPU will be pre-allocated at boot time.
* The state for each apic CPU info structure will be assigned according
* to the following rules:
* Rule 1:
* Slot index range: [0, min(apic_nproc, boot_ncpus))
* State flags: 0
* Note: cpu exists and will be configured/enabled at boot time
* Rule 2:
* Slot index range: [boot_ncpus, apic_nproc)
* State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
* Note: cpu exists but won't be configured/enabled at boot time
* Rule 3:
* Slot index range: [apic_nproc, boot_ncpus)
* State flags: APIC_CPU_FREE
* Note: cpu doesn't exist at boot time
* Rule 4:
* Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
* State flags: APIC_CPU_FREE
* Note: cpu doesn't exist at boot time
*/
CPUSET_ADD(apic_cpumask, i);
apic_cpus[i].aci_status = 0;
}
for (i = boot_ncpus; i < apic_nproc; i++) {
}
for (i = apic_nproc; i < boot_ncpus; i++) {
}
}
for (i = 0; i < apic_io_max; i++) {
ioapic_ix = i;
/*
* need to check Sitka on the following acpi problem
* On the Sitka, the ioapic's apic_id field isn't reporting
* the actual io apic id. We have reported this problem
* to Intel. Until they fix the problem, we will get the
* actual id directly from the ioapic.
*/
if (hid != apic_io_id[i]) {
if (apic_io_id[i] == 0)
apic_io_id[i] = hid;
else { /* set ioapic id to whatever reported by ACPI */
}
}
if (apic_first_avail_irq <= apic_io_vectend[i])
}
/*
* Process SCI configuration here
* An error may be returned here if
* acpi-user-options specifies legacy mode
* (no SCI, no ACPI mode)
*/
sci = -1;
/*
* Now call acpi_init() to generate namespaces
* If this fails, we don't attempt to use ACPI
* even if we were able to get a MADT above
*/
if (acpica_init() != AE_OK)
goto cleanup;
/*
* Call acpica_build_processor_map() now that we have
* ACPI namesspace access
*/
(void) acpica_build_processor_map();
/*
* Squirrel away the SCI and flags for later on
* in apic_picinit() when we're ready
*/
apic_sci_vect = sci;
goto cleanup;
/* Enable ACPI APIC interrupt routing */
if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
apic_enable_acpi = 1;
if (apic_sci_vect > 0) {
}
if (apic_use_acpi_madt_only) {
}
#if !defined(__xpv)
/*
* probe ACPI for hpet information here which is used later
* in apic_picinit().
*/
}
#endif
return (PSM_SUCCESS);
}
/* if setting APIC mode failed above, we fall through to cleanup */
}
apic_max_nproc = -1;
apic_nproc = 0;
for (i = 0; i < apic_io_max; i++) {
}
apic_io_max = 0;
acpi_iso_cnt = 0;
acpi_nmi_sp = NULL;
acpi_nmi_scnt = 0;
acpi_nmi_cp = NULL;
acpi_nmi_ccnt = 0;
return (PSM_FAILURE);
}
/*
* Handle default configuration. Fill in reqd global variables & tables
* Fill all details as MP table does not give any more info
*/
static int
{
/* Failed to probe ACPI MADT tables, disable CPU DR. */
apic_max_nproc = -1;
apic_cpus = (apic_cpus_info_t *)
goto apic_handle_defconf_fail;
CPUSET_ONLY(apic_cpumask, 0);
apic_nproc = 2;
/*
* According to the PC+MP spec 1.1, the local ids
* for the default configuration has to be 0 or 1
*/
else if (apic_cpus[0].aci_local_id == 0)
else
goto apic_handle_defconf_fail;
apic_io_id[0] = 2;
apic_io_max = 1;
if (apic_defconf >= 5) {
} else {
apic_io_ver[0] = 0;
}
return (PSM_SUCCESS);
if (apicadr)
if (apicioadr[0])
return (PSM_FAILURE);
}
/* Parse the entries in MP configuration table and collect info that we need */
static int
{
int ioapic_ix;
int warned = 0;
/*LINTED: pointer cast may result in improper alignment */
/* No need to count cpu entries if we won't use them */
if (!bypass_cpus_and_ioapics) {
/* Find max # of CPUS and allocate structure accordingly */
apic_nproc = 0;
apic_nproc < boot_ncpus) {
apic_nproc++;
"exceeded"
#if !defined(__amd64)
" for 32-bit mode"
#endif
"; Solaris will use %d CPUs.",
warned = 1;
}
}
procp++;
}
return (PSM_FAILURE);
}
/*LINTED: pointer cast may result in improper alignment */
/*
* start with index 1 as 0 needs to be filled in with Boot CPU, but
* if we're bypassing this information, it has already been filled
* in by acpi_probe(), so don't overwrite it.
*/
if (!bypass_cpus_and_ioapics)
apic_nproc = 1;
/* check whether the cpu exists or not */
if (!bypass_cpus_and_ioapics &&
if (apic_cpus[0].aci_local_id !=
return (PSM_FAILURE);
}
apic_cpus[0].aci_local_ver =
apic_nproc < boot_ncpus) {
apic_nproc++;
}
}
procp++;
}
/*
* Save start of bus entries for later use.
* Get EISA level cntrl if EISA bus is present.
* Also get the CPI bus id for single CPI bus case
*/
/*
* apic_single_pci_busid will be used only if
* apic_pic_bus_total is equal to 1
*/
}
busp++;
}
if (!bypass_cpus_and_ioapics)
apic_io_max = 0;
do {
(void *)mapin_ioapic(
if (!apicioadr[apic_io_max])
return (PSM_FAILURE);
if (apic_io_id[apic_io_max] == 0)
else {
/*
* set ioapic id to whatever
* reported by MPS
*
* may not need to set index
* again ???
* take it out and try
*/
apic_io_id[apic_io_max]) <<
24;
APIC_ID_CMD, id);
}
}
apic_io_max++;
}
}
ioapicp++;
apic_irq_translate = 1;
break;
}
intrp++;
}
return (PSM_SUCCESS);
}
{
cpu &= ~IRQ_USER_BOUND;
/* Check whether cpu id is in valid range. */
return (B_FALSE);
/*
* Check whether cpuid is in valid range if CPU DR is enabled.
*/
return (B_FALSE);
return (B_FALSE);
}
return (B_TRUE);
}
apic_get_next_bind_cpu(void)
{
int i, count;
if (apic_next_bind_cpu >= apic_nproc) {
apic_next_bind_cpu = 0;
}
i = apic_next_bind_cpu++;
if (apic_cpu_in_range(i)) {
cpuid = i;
break;
}
}
return (cpuid);
}
{
int i;
/*
* Don't assume all IO APICs in the system are the same.
*
* Set to the minimum version.
*/
for (i = 0; i < apic_io_max; i++) {
if ((apic_io_ver[i] != 0) &&
((min_io_apic_ver == 0) ||
(min_io_apic_ver >= apic_io_ver[i])))
min_io_apic_ver = apic_io_ver[i];
}
/* Assume all local APICs are of the same version. */
}
return (version);
}
static struct apic_mpfps_hdr *
{
int i;
/* Look for the pattern "_MP_" */
for (i = 0; i < len; i += 16) {
if ((*(cptr+i) == '_') &&
/*LINTED: pointer cast may result in improper alignment */
return ((struct apic_mpfps_hdr *)(cptr + i));
}
return (NULL);
}
static int
{
int i;
cksum = 0;
for (i = 0; i < len; i++)
return ((int)cksum);
}
/*
* On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
* needs special handling. We may need to chase up the device tree,
* using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
* to find the IPIN at the root bus that relates to the IPIN on the
* subsidiary bus (for ACPI or MP). We may, however, have an entry
* in the MP table or the ACPI namespace for this device itself.
* We handle both cases in the search below.
*/
/* this is the non-acpi version */
int
struct apic_io_intr **intrp)
{
int pci_irq;
int ipin;
/*CONSTCOND*/
while (1) {
return (-1);
PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
NULL) != 0)
return (-1);
/*
* This is the rotating scheme documented in the
* PCI-to-PCI spec. If the PCI-to-PCI bridge is
* behind another PCI-to-PCI bridge, then it needs
* to keep ascending until an interrupt entry is
* found or the root is reached.
*/
bridge_bus = (int)apic_single_pci_busid;
(ipin & 0x3);
bridge_bus)) != NULL) {
return (pci_irq);
}
child_ipin = ipin;
} else {
return (-1);
}
}
/*LINTED: function will not fall off the bottom */
}
{
int i;
for (i = 0; i < apic_io_max; i++) {
return ((uchar_t)i);
}
return (0xFF); /* shouldn't happen */
}
/*
* See if two irqs are compatible for sharing a vector.
* Currently we only support sharing of PCI devices.
*/
static int
{
/* Assume active high by default */
po1 = 0;
po2 = 0;
return (0);
else
po1 = AV_ACTIVE_LOW;
else
po2 = AV_ACTIVE_LOW;
return (1);
return (0);
}
struct apic_io_intr *
{
/*
* It can have more than 1 entry with same source bus IRQ,
* but unique with the source bus id
*/
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
struct mps_bus_info {
char *bus_name;
int bus_id;
} bus_info_array[] = {
"ISA ", BUS_ISA,
"PCI ", BUS_PCI,
"EISA ", BUS_EISA,
"XPRESS", BUS_XPRESS,
"PCMCIA", BUS_PCMCIA,
"VL ", BUS_VL,
"CBUS ", BUS_CBUS,
"CBUSII", BUS_CBUSII,
"FUTURE", BUS_FUTURE,
"INTERN", BUS_INTERN,
"MBI ", BUS_MBI,
"MBII ", BUS_MBII,
"MPI ", BUS_MPI,
"MPSA ", BUS_MPSA,
"NUBUS ", BUS_NUBUS,
"TC ", BUS_TC,
"VME ", BUS_VME,
"PCI-E ", BUS_PCIE
};
static int
{
int i = 0;
for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
return (bus_info_array[i].bus_id);
return (0);
}
static int
{
busp++;
}
return (0);
}
int
{
busp++;
}
bustype));
return (-1);
}
/*
* Check if a particular irq need to be reserved for any io_intr
*/
static struct apic_io_intr *
{
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
/*
* Check if the given ioapicindex intin combination has already been assigned
* an irq. If so return irqno. Else -1
*/
int
{
int i;
/* find ioapic and intin in the apic_irq_table[] and return the index */
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
irqptr = apic_irq_table[i];
while (irqptr) {
if ((irqptr->airq_mps_intr_index >= 0) &&
"entry for ioapic:intin %x:%x "
return (i);
}
}
}
return (-1);
}
int
{
int freeirq, i;
/*
* if BIOS really defines every single irq in the mps
* table, then don't worry about conflicting with
* them, just use any free slot in apic_irq_table
*/
for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
if ((apic_irq_table[i] == NULL) ||
FREE_INDEX) {
freeirq = i;
break;
}
}
if (freeirq == -1) {
/* This shouldn't happen, but just in case */
return (-1);
}
}
psm_name);
return (-1);
}
}
return (freeirq);
}
static int
{
int i;
/* Check if any I/O entry needs this IRQ */
if (apic_find_io_intr(i) == NULL) {
/* Then see if it is free */
if ((apic_irq_table[i] == NULL) ||
(apic_irq_table[i]->airq_mps_intr_index ==
FREE_INDEX)) {
return (i);
}
}
return (-1);
}
/*
* compute the polarity, trigger mode and vector for programming into
* the I/O apic and record in airq_rdt_entry.
*/
void
{
short intr_index;
if (intr_index == RESERVE_INDEX) {
return;
} else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
return;
}
/* Assume edge triggered by default */
level = 0;
/* Assume active high by default */
po = 0;
} else if (intr_index == ACPI_INDEX) {
} else
AV_LEVEL : 0;
if (level &&
po = AV_ACTIVE_LOW;
} else {
} else
AV_LEVEL : 0;
po = AV_ACTIVE_LOW;
}
if (level)
/*
* The 82489DX External APIC cannot do active low polarity interrupts.
*/
else
io_po = 0;
prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
"vector=0x%x cpu=0x%x\n\n", ioapicindex,
}
int
{
int status;
intr_flagp)) == ACPI_PSM_SUCCESS) {
"from cache for device %s, instance #%d\n", psm_name,
return (status);
}
&acpipsmlnk)) == ACPI_PSM_FAILURE) {
" acpi_translate_pci_irq failed for device %s, instance"
ddi_get_instance(dip)));
return (status);
}
if (status != ACPI_PSM_SUCCESS) {
}
}
if (status == ACPI_PSM_SUCCESS) {
intr_flagp, &acpipsmlnk);
"new irq %d for device %s, instance #%d\n", psm_name,
}
return (status);
}
/*
* Adds an entry to the irq list passed in, and returns the new list.
* Entries are added in priority order (lower numerical priorities are
* placed closer to the head of the list)
*/
static prs_irq_list_t *
{
/* ->next is NULL from kmem_zalloc */
/*
* New list -- return the new entry as the list.
*/
return (newent);
/*
* Save original list pointer for return (since we're not modifying
* the head)
*/
/*
* Insertion sort, with entries with identical keys stored AFTER
* existing entries (the less-than-or-equal test of priority does
* this for us).
*/
}
return (newent);
} else {
return (origlistp);
}
}
/*
* Frees the list passed in, deallocating all memory and leaving *listpp
* set to NULL.
*/
static void
{
}
}
/*
* apic_choose_irqs_from_prs returns a list of irqs selected from the list of
* irqs returned by the link device's _PRS method. The irqs are chosen
* to minimize contention in situations where the interrupt link device
* can be programmed to steer interrupts to different interrupt controller
* inputs (some of which may already be in use). The list is sorted in order
* of irqs to use, with the highest priority given to interrupt controller
* inputs that are not shared. When an interrupt controller input
* must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
* returned list in the order that minimizes sharing (thereby ensuring lowest
* possible latency from interrupt trigger time to ISR execution time).
*/
static prs_irq_list_t *
int crs_irq)
{
int i;
while (irqlistent != NULL) {
for (i = 0; i < irqlistent->num_irqs; i++) {
if (irq <= 0) {
/* invalid irq number */
continue;
}
continue;
/*
* If we do not prefer the current irq from _CRS
* or if we do and this irq is the same as the
* current irq from _CRS, this is the one
* to pick.
*/
return (prsirqlistp);
}
continue;
}
/*
* Edge-triggered interrupts cannot be shared
*/
continue;
/*
* To work around BIOSes that contain incorrect
* interrupt polarity information in interrupt
* descriptors returned by _PRS, we assume that
* the polarity of the other device sharing this
* interrupt controller input is compatible.
* If it's not, the caller will catch it when
* the caller invokes the link device's _CRS method
* (after invoking its _SRS method).
*/
if (!acpi_intr_compatible(iflags,
"not compatible [%x:%x:%x !~ %x:%x:%x]",
continue;
}
/*
* If we prefer the irq from _CRS, no need
* to search any further (and make sure
* to add this irq with the highest priority
* so it's tried first).
*/
return (acpi_insert_prs_irq_ent(
0 /* Highest priority */,
&irqlistent->acpi_prs_prv));
}
/*
* Priority is equal to the share count (lower
* share count is higher priority). Note that
* the intr flags passed in here are the ones we
* changed above -- if incorrect, it will be
* caught by the caller's _CRS flags comparison.
*/
}
/* Go to the next irqlist entry */
}
return (prsirqlistp);
}
/*
* Configures the irq for the interrupt link device identified by
* acpipsmlnkp.
*
* Gets the current and the list of possible irq settings for the
* device. If apic_unconditional_srs is not set, and the current
* resource setting is in the list of possible irq settings,
* current irq resource setting is passed to the caller.
*
* Otherwise, picks an irq number from the list of possible irq
* settings, and sets the irq of the device to this value.
* If prefer_crs is set, among a set of irq numbers in the list that have
* the least number of devices sharing the interrupt, we pick current irq
* resource setting if it is a member of this set.
*
* Passes the irq number in the value pointed to by pci_irqp, and
* polarity and sensitivity in the structure pointed to by dipintrflagp
* to the caller.
*
* Note that if setting the irq resource failed, but successfuly obtained
* the current irq resource settings, passes the current irq resources
* and considers it a success.
*
* Returns:
* ACPI_PSM_SUCCESS on success.
*
* ACPI_PSM_FAILURE if an error occured during the configuration or
* if a suitable irq was not found for this device, or if setting the
* irq resource and obtaining the current resource fails.
*
*/
static int
{
== ACPI_PSM_FAILURE) {
"or assign IRQ for device %s, instance #%d: The system was "
"unable to get the list of potential IRQs from ACPI.",
return (ACPI_PSM_FAILURE);
}
(cur_irq > 0)) {
/*
* If an IRQ is set in CRS and that IRQ exists in the set
* returned from _PRS, return that IRQ, otherwise print
* a warning
*/
== ACPI_PSM_SUCCESS) {
return (ACPI_PSM_SUCCESS);
}
"current irq %d for device %s, instance #%d in ACPI's "
"list of possible irqs for this device. Picking one from "
ddi_get_instance(dip)));
}
"suitable irq from the list of possible irqs for device "
"%s, instance #%d in ACPI's list of possible irqs",
return (ACPI_PSM_FAILURE);
}
for (prs_irq_entp = prs_irq_listp;
== ACPI_PSM_SUCCESS) {
/*
* setting irq was successful, check to make sure CRS
* reflects that. If CRS does not agree with what we
* set, return the irq that was set.
*/
dipintr_flagp) == ACPI_PSM_SUCCESS) {
"!%s: IRQ resource set "
"(irqno %d) for device %s "
"instance #%d, differs from "
"current setting irqno %d",
} else {
/*
* On at least one system, there was a bug in
* a DSDT method called by _STA, causing _STA to
* indicate that the link device was disabled
* (when, in fact, it was enabled). Since _SRS
* succeeded, assume that _CRS is lying and use
* the iflags from this _PRS interrupt choice.
* If we're wrong about the flags, the polarity
* will be incorrect and we may get an interrupt
* storm, but there's not much else we can do
* at this point.
*/
}
/*
* Return the irq that was set, and not what _CRS
* reports, since _CRS has been seen to return
* different IRQs than what was passed to _SRS on some
* systems (and just not return successfully on others).
*/
} else {
"irq %d failed for device %s instance #%d",
ddi_get_instance(dip)));
if (cur_irq == -1) {
return (ACPI_PSM_FAILURE);
}
}
}
if (!found_irq)
return (ACPI_PSM_FAILURE);
return (ACPI_PSM_SUCCESS);
}
void
{
int ioapic_ix;
int intin_max;
int intin_ix;
/* Disable the I/O APIC redirection entries */
/* Bits 23-16 define the maximum redirection entries */
& 0xff;
/*
* The assumption here is that this is safe, even for
* systems with IOAPICs that suffer from the hardware
* erratum because all devices have been quiesced before
* this function is called from apic_shutdown()
* (or equivalent). If that assumption turns out to be
* false, this mask operation can induce the same
* erratum result we're trying to avoid.
*/
AV_MASK);
}
}
}
/*
* Looks for an IOAPIC with the specified physical address in the /ioapics
* node in the device tree (created by the PCI enumerator).
*/
static boolean_t
{
/*
* Look in /ioapics, for the ioapic with
* the physical address given
*/
if (ioapicsnode == NULL)
return (B_FALSE);
/* Load first child: */
!= 0 && physaddr == ioapic_paddr) {
IOAPICS_PROP_DEVID, 0);
if (did == DEVID_8131_IOAPIC ||
did == DEVID_8132_IOAPIC) {
}
}
}
if (!done)
}
/* The ioapics node was held by ddi_find_devinfo, so release it */
return (rv);
}
struct apic_state {
};
static int
apic_acpi_enter_apicmode(void)
{
/* Setup parameter object */
if (ACPI_FAILURE(status))
return (PSM_FAILURE);
else
return (PSM_SUCCESS);
}
static void
{
int i, cpuid;
/*
* First the local APIC.
*/
if (apic_mode == LOCAL_APIC)
/*
* If on the boot processor then save the IOAPICs' IDs
*/
if ((cpuid = psm_get_cpu_id()) == 0) {
iflag = intr_clear();
for (i = 0; i < apic_io_max; i++)
}
}
static void
{
int i;
/*
* First the local APIC.
*/
if (apic_mode == LOCAL_APIC) {
}
/*
* the following only needs to be done once, so we do it on the
* boot processor, since we know that we only have one of those
*/
if (psm_get_cpu_id() == 0) {
iflag = intr_clear();
/* Restore IOAPICs' APIC IDs */
for (i = 0; i < apic_io_max; i++) {
}
/*
* Reenter APIC mode before restoring LNK devices
*/
(void) apic_acpi_enter_apicmode();
/*
* restore acpi link device mappings
*/
}
}
/*
* Returns 0 on success
*/
int
{
case PSM_STATE_ALLOC:
return (ENOMEM);
sizeof (struct apic_state);
return (0);
case PSM_STATE_FREE:
return (0);
case PSM_STATE_SAVE:
return (0);
case PSM_STATE_RESTORE:
return (0);
default:
return (EINVAL);
}
}