/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_USB_UHCID_H
#define _SYS_USB_UHCID_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Universal Host Controller Driver (UHCI)
*
* The UHCI driver is a driver which interfaces to the Universal
* Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
* the Host Controller is defined by the Universal Host Controller Interface.
*
* This file contains the data structures for the UHCI driver.
*/
/* limit the xfer size for bulk */
/* Maximum allowable data transfer size per transaction */
/*
* Generic UHCI Macro definitions
*/
/* Default time out values for bulk and ctrl commands */
/* UHCI root hub structure */
typedef struct uhci_root_hub_info {
/* Last status of ports */
/*
* UHCI Host Controller per instance data structure
*
* The Host Controller Driver (HCD) maintains the state of Host Controller
* (HC). There is an uhci_state structure per instance of the UHCI
* host controller.
*/
typedef struct uhci_state {
/* UHCI Host Controller Software State information */
/* Frame interval reg */
/*
* There are two pools of memory. One pool contains the memory for
* the transfer descriptors and other pool contains the memory for
* the Queue Head pointers. The advantage of the pools is that it's
* easy to go back and forth between the iommu and the cpu addresses.
*
* The pools are protected by the int_mutex because the memory
* in the pools may be accessed by either the host controller or the
* host controller driver.
*/
/* General transfer descriptor pool */
/* Endpoint descriptor pool */
/* Semaphore to serialize opens and closes */
/* Timeout id of the root hub status change pipe handler */
/*
* Bandwidth fields
*
* The uhci_bandwidth array keeps track of the allocated bandwidth
* for this host controller. The uhci_bandwidth_isoch_sum field
* represents the sum of the allocated isochronous bandwidth. The
* total bandwidth allocated for least allocated list out of the 32
* interrupt lists is represented by the uhci_bandwdith_intr_min
* field.
*/
/* Polled I/O support */
/* Software frame number */
/* Number of pending bulk commands */
/* logging support */
/*
* TD's used for the generation of interrupt
*/
/*
* Keep io base address, for debugging purpose
*/
/*
* kstat structures
*/
} uhci_state_t;
/*
* uhci_dma_addr_bind_flag values
*
* This flag indicates if the various DMA addresses allocated by the UHCI
* have been bound to their respective handles. This is needed to recover
* without errors from uhci_cleanup when it calls ddi_dma_unbind_handle()
*/
/*
* Definitions for uhci_polled_flag
* The flag is set to UHCI_POLLED_FLAG_FALSE by default. The flags is
* set to UHCI_POLLED_FLAG_TD_COMPL when shifting from normal mode to
* polled mode and if the normal TD is completed at that time. And the
* flag is set to UHCI_POLLED_FLAG_TRUE while exiting from the polled
* mode. In the timeout handler for root hub status change, this flag
* is checked. If set to UHCI_POLLED_FLAG_TRUE, the routine
* uhci_process_submitted_td_queue() to process the completed TD.
*/
#define UHCI_POLLED_FLAG_FALSE 0
/*
* Pipe private structure
*
* There is an instance of this structure per pipe. This structure holds
* HCD specific pipe information. A pointer to this structure is kept in
* the USBA pipe handle (usba_pipe_handle_data_t).
*/
typedef struct uhci_pipe_private {
/*
* Each pipe may have multiple transfer wrappers. Each transfer
* wrapper represents a USB transfer on the bus. A transfer is
* made up of one or more transactions.
*/
/*
* Starting frame number at which next isoc TD will be inserted
* for this pipe
*/
/*
* HCD gets Interrupt/Isochronous IN polling request only once and
* it has to insert next polling requests after completion of first
* has to take copy of the original Interrupt/Isochronous IN request.
*/
/* warlock directives, stable data */
/*
* Pipe states
*
* uhci pipe states will be similar to usba. Refer usbai.h.
*/
/*
* IN packets that are pending
*/
/* Function prototype */
/*
* Transfer wrapper
*
* The transfer wrapper represents a USB transfer on the bus and there
* is one instance per USB transfer. A transfer is made up of one or
* more transactions. UHCI uses one TD for one transaction. So one
* transfer wrapper may have one or more TDs associated.
*
* Control and bulk pipes will have one transfer wrapper per transfer
* and where as Isochronous and Interrupt pipes will only have one
* transfer wrapper. The transfers wrapper are continually reused for
* the Interrupt and Isochronous pipes as those pipes are polled.
*
* Control, bulk and interrupt transfers will have one DMA buffer per
* transfer. The data to be transferred are contained in the DMA buffer
* which is virtually contiguous but physically discontiguous. When
* preparing the TDs for a USB transfer, the DMA cookies contained in
* the buffer need to be walked through to retrieve the DMA addresses.
*
* Isochronous transfers will have multiple DMA buffers per transfer
* with each isoc packet having a DMA buffer. And the DMA buffers should
* only contain one cookie each, so no cookie walking is necessary.
*/
typedef struct uhci_trans_wrapper {
/*
* This is the function to call when this td is done. This way
* we don't have to look in the td to figure out what kind it is.
*/
/*
* This is the callback value used when processing a done td.
*/
/* Maximum amount of time for this command */
/* This is used to avoid multiple tw deallocation */
/*
* Pointer to the data in case of send command
*/
/* save a copy of current request */
/* Macros for uhci DMA buffer */
/*
* Macro for allocation of Bulk and Isoc TD pools
*
* When a Bulk or Isoc transfer needs to allocate too many TDs,
* the allocation for one physical contiguous TD pool may fail
* due to the fragmentation of physical memory. The number of
* TDs in one pool should be limited so that a TD pool is within
* page size under this situation.
*/
#if defined(__sparc)
#else
#endif
/* set timeout flag so as to decrement timeout_cnt only once */
/* Macro for changing the data toggle */
/*
*/
(char *)uhcip->uhci_qh_pool_addr))
(char *)(x)->pool_addr))
(char *)uhcip->uhci_td_pool_addr))
/*
* If the terminate bit is cleared, there shouldn't be any
* race condition problems. If the host controller reads the
* bit before the driver has a chance to set the bit, the bit
* will be reread on the next frame.
*/
/*
* for HCD based kstats:
* uhci_intrs_stats_t structure
*/
typedef struct uhci_intrs_stats {
/*
* uhci defines for kstats
*/
/*
* Host Contoller Software States
*
* UHCI_CTLR_INIT_STATE:
* The host controller soft state will be set to this during the
* uhci_attach.
*
* UHCI_CTLR_SUSPEND_STATE:
* The host controller soft state will be set to this during the
* uhci_cpr_suspend.
*
* UHCI_CTLR_OPERATIONAL_STATE:
* The host controller soft state will be set to this after moving
* host controller to operational state and host controller start
* generating SOF successfully.
*
* UHCI_CTLR_ERROR_STATE:
* The host controller soft state will be set to this during the
* hardware error or no SOF conditions.
*
* Under non-operational state, only pipe stop polling, pipe reset
* and pipe close are allowed. But all other entry points like pipe
*/
/*
* Debug printing Masks
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_USB_UHCID_H */