uhci.h revision d29f5a711240f866521445b1656d114da090335e
2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License (the "License"). 2N/A * You may not use this file except in compliance with the License. 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2N/A * Use is subject to license terms. 2N/A * Universal Host Controller Driver (UHCI) 2N/A * The UHCI driver is a driver which interfaces to the Universal 2N/A * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 2N/A * the Host Controller is defined by the Universal Host Controller 2N/A * The register set of the UCHI controller 2N/A * This structure is laid out for proper alignment so no need to pack(1). 2N/A * #defines for the USB Command Register 2N/A * #defines for the USB Status Register 2N/A * #defines for the USB Root Hub Port Register 2N/A * #defines for USB Interrupt Enable Register 2N/A * UHCI Queue Head structure, aligned on 16 byte boundary 2N/A /* Hardware controlled bits */ 2N/A /* Software controlled bits */ 2N/A (((v) & ((
1U<<l)-
1)) << o))
2N/A * UHCI Transfer Descriptor structure, aligned on 16 byte boundary 2N/A /* Information required by HC for executing the request */ 2N/A /* Data buffer address */ 2N/A /* Information required by HCD for managing the request */ 2N/A/* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */ 2N/A * These provide synchronization between TD deletions. 2N/A * Structure for Bulk and Isoc TD pools 2N/A * Structure for Bulk and Isoc transfers 2N/A * Structure for Isoc DMA buffer 2N/A * One Isoc transfer includes multiple Isoc packets. 2N/A * One DMA buffer is allocated for one packet each. 2N/A * Macros related to ISOC transfers 2N/A * Bandwidth allocation 2N/A * The following definitions are used during bandwidth 2N/A * calculations for a given endpoint maximum packet size. 2N/A#
define SOF 6 /* Length in bytes of SOF */ 2N/A#
define EOF 2 /* Length in bytes of EOF */ 2N/A * Minimum polling interval for low speed endpoint 2N/A * According USB Specifications, a full-speed endpoint can specify 2N/A * a desired polling interval 1ms to 255ms and a low speed endpoints 2N/A * are limited to specifying only 10ms to 255ms. But some old keyboards 2N/A * and mice uses polling interval of 8ms. For compatibility purpose, 2N/A * we are using polling interval between 8ms and 255ms for low speed 2N/A * For non-periodic transfers, reserve at least for one low-speed device 2N/A * transaction and according to USB Bandwidth Analysis white paper, it 2N/A * comes around 12% of USB frame time. Then periodic transfers will get 2N/A * 88% of USB frame time. 2N/A * The following are the protocol overheads in terms of Bytes for the 2N/A * different transfer types. All these protocol overhead values are 2N/A * derived from the 5.9.3 section of USB Specification and with the 2N/A * help of Bandwidth Analysis white paper which is posted on the USB 2N/A * The Host Controller (HC) delays are the USB host controller specific 2N/A * delays. The value shown below is the host controller delay for the 2N/A * Sand core USB host controller. 2N/A * The low speed clock below represents that to transmit one low-speed 2N/A * bit takes eight times more than one full speed bit time. 2N/A/* the 16 byte alignment is required for every TD and QH start addr */ 2N/A#
endif /* _SYS_USB_UHCI_H */