/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_USB_UHCI_H
#define _SYS_USB_UHCI_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Universal Host Controller Driver (UHCI)
*
* The UHCI driver is a driver which interfaces to the Universal
* Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
* the Host Controller is defined by the Universal Host Controller
* Interface spec.
*/
/*
* The register set of the UCHI controller
* This structure is laid out for proper alignment so no need to pack(1).
*/
typedef volatile struct hcr_regs {
} hc_regs_t;
/*
* #defines for the USB Command Register
*/
/*
* #defines for the USB Status Register
*/
/*
* #defines for the USB Root Hub Port Register
*/
/*
* #defines for USB Interrupt Enable Register
*/
/*
* UHCI Queue Head structure, aligned on 16 byte boundary
*/
typedef struct uhci_qh {
/* Hardware controlled bits */
/* Software controlled bits */
} queue_head_t;
(((v) & ((1U<<l)-1)) << o))
/*
* UHCI Transfer Descriptor structure, aligned on 16 byte boundary
*/
typedef struct uhci_td {
/* Information required by HC for executing the request */
/* Data buffer address */
/* Information required by HCD for managing the request */
} uhci_td_t;
/* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */
/*
* These provide synchronization between TD deletions.
*/
/*
* Structure for Bulk and Isoc TD pools
*/
typedef struct uhci_bulk_isoc_td_pool {
/*
* Structure for Bulk and Isoc transfers
*/
typedef struct uhci_bulk_isoc_xfer_info {
/*
* Structure for Isoc DMA buffer
* One Isoc transfer includes multiple Isoc packets.
* One DMA buffer is allocated for one packet each.
*/
typedef struct uhci_isoc_buf {
/*
* Macros related to ISOC transfers
*/
#define INVALID_FRNUM 0
/*
* Bandwidth allocation
* The following definitions are used during bandwidth
* calculations for a given endpoint maximum packet size.
*/
/*
* Minimum polling interval for low speed endpoint
*
* According USB Specifications, a full-speed endpoint can specify
* a desired polling interval 1ms to 255ms and a low speed endpoints
* are limited to specifying only 10ms to 255ms. But some old keyboards
* and mice uses polling interval of 8ms. For compatibility purpose,
* we are using polling interval between 8ms and 255ms for low speed
* endpoints.
*/
/*
* For non-periodic transfers, reserve at least for one low-speed device
* transaction and according to USB Bandwidth Analysis white paper, it
* comes around 12% of USB frame time. Then periodic transfers will get
* 88% of USB frame time.
*/
/*
* The following are the protocol overheads in terms of Bytes for the
* different transfer types. All these protocol overhead values are
* derived from the 5.9.3 section of USB Specification and with the
* help of Bandwidth Analysis white paper which is posted on the USB
* developer forum.
*/
/*
* The Host Controller (HC) delays are the USB host controller specific
* delays. The value shown below is the host controller delay for the
* Sand core USB host controller.
*/
/*
* The low speed clock below represents that to transmit one low-speed
* bit takes eight times more than one full speed bit time.
*/
/* the 16 byte alignment is required for every TD and QH start addr */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_USB_UHCI_H */