/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_USB_OHCI_H
#define _SYS_USB_OHCI_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Open Host Controller Driver (OHCI)
*
* The USB Open Host Controller driver is a software driver which interfaces
* to the Universal Serial Bus layer (USBA) and the USB Open Host Controller.
* The interface to USB Open Host Controller is defined by the OpenHCI Host
* Controller Interface.
*
* This header file describes the registers and data structures shared by the
* USB Open Host Controller and the USB Open Host Controller Driver.
*/
#include <sys/ndi_impldefs.h>
/*
* Each OHCI buffer can hold upto 8k bytes of data. Hence there is a
* restriction of 4k alignment while allocating a dma buffer.
*/
/*
* USB Host controller DMA scatter gather list defines for
* Sparc and non-sparc architectures.
*/
#if defined(__sparc)
#else
#endif
/*
* According to the OHCI spec ED and TD need to be 16 byte aligned.
* However, iTD needs to be 32 byte aligned. Since we do not
* distinguish between iTD and TD, make them both 32 byte aligned.
*
* ED = 16 byte aligned
* TD = 32 byte aligned
* HCCA = 256 byte aligned
*/
/*
* Vendor id and Device id for ULI1575 southbridge.
*/
/*
* Need a workaround for ULI1575 chipset. Following OHCI
* Operational Memory Registers are not cleared to their
* default value on reset. Explicitly set the registers
* to default value after reset.
*/
/*
* OpenHCI Operational Registers
*
* The Host Controller (HC) contains a set of on-chip operational registers
* which are mapped into a noncacheable portion of the system addressable
* space and these registers are also used by the Host Controller Driver
* (HCD).
*/
typedef volatile struct ohci_regs {
/* Control and status registers */
/* Memory pointer registers */
/* Frame counter registers */
/* Root hub registers */
} ohci_regs_t;
/* hcr_revision bits */
/* hcr_control bits */
/* Values for the Host Controller Functional State bits (HCR_CONTROL_HCFS) */
/* hcr_cmd_status bits */
/* hcr_intr_status bits and hcr_intr_mask bits */
/* hcr_frame_interval bits */
/* hcr_frame_remaining bits */
/* hcr_transfer_ls */
/* hcr_rh_descriptorA bits */
/* hcr_rh_descriptorB bits */
/* hcr_rh_status bits */
/* hcr_rh_portstatus bits */
/*
* Host Controller Communications Area
*
* The Host Controller Communications Area (HCCA) is a 256-byte structre
* of system memory that is established by the Host Controller Driver (HCD)
* and this structre is used for communication between HCD and HC. The HCD
* maintains a pointer to this structure in the Host Controller (HC). This
* structure must be aligned to a 256-byte boundary.
*/
typedef volatile struct ohci_hcca {
/* Ptrs to ohci_ed */
} ohci_hcca_t;
/*
* Host Controller Endpoint Descriptor
*
* An Endpoint Descriptor (ED) is a memory structure that describes the
* information necessary for the Host Controller (HC) to communicate with
* a device endpoint. An ED includes a Transfer Descriptor (TD) pointer.
* This structure must be aligned to a 16 byte boundary.
*/
typedef volatile struct ohci_ed {
} ohci_ed_t;
/*
* hc_endpoint_descriptor control bits
*/
/*
* hced_state
*
* ED states
*/
/*
* Host Controller Transfer Descriptor
*
* A Transfer Descriptor (TD) is a memory structure that describes the
* information necessary for the Host Controller (HC) to transfer a block
* of data to or from a device endpoint. These TD's will be attached to
* a Endpoint Descriptor (ED). This structure includes the fields for both
* General and Isochronous Transfer Descriptors. The General TDs must be
* aligned to 16 byte, where as Isochronous TDs must be aligned to 32 byte.
*/
typedef volatile struct ohci_td {
/* Used only for isoch */
} ohci_td_t;
/*
* Common hc_td control bits both for the General and Isochronous Transfer
* Descriptors.
*/
/*
* hc_td control bits specific to Isochronous Transfer Descriptors.
*/
/*
* Condition codes both to General and Isochronous Transfer Descriptors.
* Even these condition codes are valid for offsets of the isochronous
* transfer descriptos.
*/
/*
* Condition codes specific to Isochronous Transfer Descriptors.
*/
/*
* hctd_state
*
* TD States
*/
/*
* hctd_ctrl_phase
*
* Control Transfer Phase information
*/
/*
* Structure for Isoc DMA buffer
* One Isoc transfer includes multiple Isoc packets and need to be
* transfered in multiple TDs.
* One DMA buffer is allocated for one Isoc TD which may hold up
* to eight Isoc packets.
*/
typedef struct ohci_isoc_buf {
#ifdef __cplusplus
}
#endif
#endif /* _SYS_USB_OHCI_H */