/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_USB_EHCI_H
#define _SYS_USB_EHCI_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Enhanced Host Controller Driver (EHCI)
*
* The EHCI driver is a software driver which interfaces to the Universal
* Serial Bus layer (USBA) and the Host Controller (HC). The interface to
* the Host Controller is defined by the EHCI Host Controller Interface.
*
* This header file describes the registers and data structures shared by
* the EHCI USB controller (HC) and the EHCI Driver.
*/
#include <sys/ndi_impldefs.h>
/*
* Each EHCI buffer can hold upto 4k bytes of data. Hence there is a
* restriction of 4k alignment while allocating a dma buffer.
*/
/*
* USB Host controller DMA scatter gather list defines for
* Sparc and non-sparc architectures.
*/
#if defined(__sparc)
#else
#endif
/* Set the default data structure (QTD,QH,SITD,ITD) to a 32 byte alignment */
/*
* EHCI Capability Registers
*
* The registers specify the limits, restrictions and capabilities of the
* specific EHCI Host Controller implementation.
*/
typedef volatile struct ehci_caps {
} ehci_caps_t;
/*
* EHCI revision
*
* EHCI driver supports EHCI host controllers compliant to 0.95 and higher
* revisions of EHCI specifications.
*/
/* EHCI HCS Params Register Bits */
/* EHCI HCC Params Register Bits */
/* EHCI Port Route Register Bits */
/*
* EHCI Operational Registers
*
* The EHCI Host Controller contains a set of on-chip operational registers
* which are mapped into a non-cacheable portion of the system addressable
* space. These registers are also used by the EHCI Host Controller Driver.
* This structure must be aligned to 32 byte boundary.
*/
typedef volatile struct ehci_regs {
/* Control and status registers */
/* Memory pointer registers */
/* Root hub registers */
/* Root hub port status and control information */
} ehci_regs_t;
/* EHCI Command Register Bits */
/* EHCI Status Register Bits */
/* EHCI Interrupt Register Bits */
/* EHCI Frame Index Register Bits */
/* EHCI Control Data Structure Segment Register Bits */
/* Most significant 32 bits for all EHCI data structures in 64bit addressing */
/* EHCI Periodic Frame List Base Address Register Bits */
/* EHCI Asynchronous List Address Register Bits */
/* EHCI Config Flag Register Bits */
/* EHCI Root Hub Port Status and Control Register Bits */
/* Root hub port change bits mask */
/*
* EHCI Extended Capability Registers
*
* Currently this register only specifies BIOS handoff information.
*/
#define EHCI_EX_CAP_ID_SHIFT 0
/*
* Host Controller Periodic Frame List Area
*
* The Host Controller Periodic Frame List Area is a 4K structre of system
* memory that is established by the Host Controller Driver (HCD) and this
* structre is used for communication between HCD and HC. The HCD maintains
* a pointer to this structure in the Host Controller (HC). This structure
* must be aligned to a 4K boundary. There are 1024 periodic frame list
* entries.
*/
typedef volatile struct ehci_periodic_frame_list {
EHCI_NUM_PERIODIC_FRAME_LISTS]; /* 1024 lists */
/*
* Host Controller Queue Head
*
* An Queue Head (QH) is a memory structure that describes the information
* necessary for the Host Controller to communicate with a device endpoint
* except High Speed and Full Speed Isochronous's endpoints. An QH includes
* a Queue Element Transfer Descriptor (QTD) pointer. This structure must
* be aligned to a 32 byte boundary.
*/
typedef volatile struct ehci_qh {
/* Endpoint capabilities or characteristics */
/* Tranfer overlay */
/* HCD private fields */
} ehci_qh_t;
/*
* qh_link_ptr control bits.
*/
/*
* qh_ctrl control bits.
*/
/*
* q_split_ctrl control bits.
*/
/*
* qh_curr_qtd control bits.
*/
/*
* qh_next_qtd control bits.
*/
/*
* qh_alt_next_qtd control bits.
*/
/*
* qh_status control bits.
*/
/*
* qh_buf[X] control bits.
*/
/*
* qh_buf_high[X] control bits.
*/
/*
* qh_state
*
* QH States
*/
/*
* Host Controller Queue Element Transfer Descriptor
*
* A Queue Element Transfer Descriptor (QTD) is a memory structure that
* describes the information necessary for the Host Controller (HC) to
* transfer a block of data to or from a device endpoint except High
* Speed and Full Speed Isochronous's endpoints. These QTD's will be
* attached to a Queue Head (QH). This structure must be aligned to a
* 32 byte boundary.
*/
typedef volatile struct ehci_qtd {
/* HCD private fields */
} ehci_qtd_t;
/*
* qtd_next_qtd control bits.
*/
/*
* qtd_alt_next_qtd control bits.
*/
/*
* qtd_ctrl control bits.
*/
/*
* qtd_buf[X] control bits.
*/
/*
* qtd_buf_high[X] control bits.
*/
/*
* qtd_state
*
* QTD States
*/
/*
* qtd_ctrl_phase
*
* Control Transfer Phase information
*/
/*
* Host Controller Split Isochronous Transfer Descripter
*
* the Host Controller (HC) to transfer a block of data to or from a
* the periodic frame list and the interrupt tree lattice. This structure
* must be aligned to a 32 byte boundary.
*/
typedef volatile struct ehci_itd {
/* Padding required */
/* HCD private fields */
} ehci_itd_t;
/*
* Generic Link Ptr Bits
* EHCI_TD_LINK_PTR : Points to the next data object to be processed
* EHCI_TD_LINK_PTR_TYPE : Type of reference this descriptor is
* EHCI_TD_LINK_PTR_VALID : Is this link pointer valid
*/
/*
* iTD Transaction Status and Control bits
*/
/*
* iTD Buffer Page Pointer bits
*/
/* Unused iTD index */
#define EHCI_SITD_CTRL 0
/*
* sitd_ctrl bits
* EHCI_SITD_CTRL_DIR : Direction of transaction
* EHCI_SITD_CTRL_PORT_MASK : Port # of recipient transaction translator(TT)
* EHCI_SITD_CTRL_HUB_MASK : Device address of the TT's hub
*/
#define EHCI_SITD_CTRL_DEVICE_SHIFT 0
/*
* sitd_uframe_sched bits
* EHCI_SITD_UFRAME_CMASK_MASK : Determines which uFrame the HC executes CSplit
* EHCI_SITD_UFRAME_SMASK_MASK : Determines which uFrame the HC executes SSplit
*/
#define EHCI_SITD_UFRAME_SMASK_SHIFT 0
/*
* sitd_xfer_state bits
* EHCI_SITD_XFER_IOC_MASK : Interrupt when transaction is complete.
* EHCI_SITD_XFER_PAGE_MASK : Which data page pointer should be concatenated
* with the CurrentOffset to construct a data
* buffer pointer
* EHCI_SITD_XFER_TOTAL_MASK : Total number of bytes expected in xfer(1023 Max).
* EHCI_SITD_XFER_CPROG_MASK : HC tracks which CSplit has been executed.
* EHCI_SITD_XFER_STATUS_MASK : Status of xfer
*/
#define EHCI_SITD_XFER_STATUS_SHIFT 0
/*
* sitd_xfer_buffer0/1
* EHCI_SITD_XFER_BUFFER_MASK : Buffer Pointer List
* EHCI_SITD_XFER_OFFSET_MASK : Current byte offset
* EHCI_SITD_XFER_TP_MASK : Transaction position
* EHCI_SITD_XFER_TCOUNT_MASK : Transaction count
*/
#define EHCI_SITD_XFER_OFFSET_SHIFT 0
#define EHCI_SITD_XFER_TCOUNT_SHIFT 0
/*
* qtd_state
*
* ITD States
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_USB_EHCI_H */