/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/*
* PMC 8x6G register definitions
*/
#ifndef _PMCS_REG_H
#define _PMCS_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Constants
*/
#define PMCS_PM8001_REV_A 0
/*
* PCIe BARs - 4 64KB memory regions
*
* BAR0-1 64KiB
* BAR2-3 64KiB
* BAR4 64KiB
* BAR5 64KiB
*/
/*
* The PMC 8x6G registers are defined by BARs in PCIe space.
*
* Four memory region BARS are used.
*
* The first is for the Messaging Unit.
*
* Top-Level registers.
*
* The third 64KiB region is a 64KiB window on the rest of the chip registers
* which can be shifted by writing a register in the second region.
*
* The fourth 64KiB region is for the message passing area.
*/
/*
* Messaging Unit Register Offsets
*/
/*
* Inbound Doorbell and Doorbell Clear Definitions
* NB: The Doorbell Clear register is only used on RevA/8000 parts.
*/
/*
* Outbound Doorbell and Doorbell Clear Register
*
* The Doorbell Clear register is only used on RevA/8000 parts.
*
* Each bit of the ODR is mapped 1-to-1 to a MSI or MSI-X vector
* table entry. There are 32 MSI and 16 MSI-X entries. The top
* 16 bits are mapped to the low 16 bits for MSI-X. For legacy
* INT-X, any bit will generate a host interrupt.
*
* Each bit in the Outbound Doorbell Clear is used to clear the
* corresponding bit in the ODR. For INT-X it also then deasserts
* any interrupt condition.
*/
/*
* Scratchpad 0 Definitions
*
* When the AAP is ready state (see Scratchpad 1), bits 31:26 is the offset
* within PCIe space for another BAR that, when mapped, will point to a region
* that conains the MPI Configuration table (the offset of which is in bits
* 25:0 of this register)
*
* When the AAP is in error state, this register contains additional error
* information.
*/
/*
* Scratchpad 1 Definitions
*
* The bottom two bits are the AAP state of the 8x6G.
*
* When the AAP is in error state, bits 31:10 contain the error indicator.
*
*/
#define PMCS_MSGU_AAP_STATE_POR 0
/*
* Scratchpad 2 Definitions
*
* Bits 31:10 contain error information if the IOP is in error state.
*/
#define PMCS_MSGU_IOP_STATE_POR 0
/*
* Scratchpad 3 Definitions
*
* Contains additional error information if the IOP is in error state
* (see Scratchpad 2)
*/
/*
* Host Scratchpad 0
* Soft Reset Signature
*/
/*
* Host Scratchpad 1
*
* This is a bit mask for freeze or unfreeze operations for IQs 0..31
*/
/*
* Host Scratchpad 2
*
* This is a bit mask for freeze or unfreeze operations for IQs 32..63
*/
/*
* Outbound Doorbell Mask Register
*
* Each bit set here masks bits and interrupt assertion for the corresponding
* bit (and vector) in the ODR.
*/
/*
* GSM Registers
*/
/*
* GSM Share Memory, IO Status Table and Ring Buffer
*/
/*
* GSM Configuration and Reset Bits
*/
#define PMCS_SOFT_RESET_BITS \
/*
* PMCS PCI Configuration Registers
*/
/*
* Top Level Registers
*/
/* these registers are in MEMBASE-III */
/* these registers are in MEMBASE-II */
/*
* Chip Reset Register Bits (PMCS_SPC_RESET)
*
* NB: all bits are inverted. That is, the normal state is '1'.
* When '0' is set, the action is taken.
*/
/*
* Timer Enables Register
*/
/*
* Special register (MEMBASE-III) for Step 5.5 in soft reset sequence to set
* GPIO into tri-state mode (temporary workaround for 1.07.xx beta firmware)
*/
/*
* These are in MEMBASE-III (i.e. in GSM space)
*/
/*
* Register Access Inline Functions
*/
#ifdef __cplusplus
}
#endif
#endif /* _PMCS_REG_H */