f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER START
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The contents of this file are subject to the terms of the
f94c602698937f2fc025056c894e5a769f39d8fejj * Common Development and Distribution License (the "License").
f94c602698937f2fc025056c894e5a769f39d8fejj * You may not use this file except in compliance with the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * or http://www.opensolaris.org/os/licensing.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * See the License for the specific language governing permissions
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * and limitations under the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * When distributing Covered Code, include this CDDL HEADER in each
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * If applicable, add the following below this CDDL HEADER, with the
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * fields enclosed by brackets "[]" replaced with your own identifying
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * information: Portions Copyright [yyyy] [name of copyright owner]
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER END
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * Use is subject to license terms.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifndef _SYS_PCIE_H
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define _SYS_PCIE_H
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifdef __cplusplus
f8d2de6bd2421da1926f3daa456d161670decdf7jchuextern "C" {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#include <sys/pci.h>
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * PCI Express capability registers in PCI configuration space relative to
70025d765b044c6d8594bb965a2247a61e991a99johnny * the PCI Express Capability structure.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_CAP_ID PCI_CAP_ID
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_CAP_NEXT_PTR PCI_CAP_NEXT_PTR
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP 0x02 /* PCI-e Capability Reg */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP 0x04 /* Device Capability */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL 0x08 /* Device Control */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS 0x0A /* Device Status */
92e1ac0d7d0f8596dfc8b9e1302e1100e5b35efajj#define PCIE_LINKCAP 0x0C /* Link Capability */
92e1ac0d7d0f8596dfc8b9e1302e1100e5b35efajj#define PCIE_LINKCTL 0x10 /* Link Control */
92e1ac0d7d0f8596dfc8b9e1302e1100e5b35efajj#define PCIE_LINKSTS 0x12 /* Link Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP 0x14 /* Slot Capability */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL 0x18 /* Slot Control */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS 0x1A /* Slot Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTCTL 0x1C /* Root Control */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTSTS 0x20 /* Root Status */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2 0x24 /* Device Capability 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2 0x28 /* Device Control 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVSTS2 0x2A /* Device Status 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_LINKCAP2 0x2C /* Link Capability 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_LINKCTL2 0x30 /* Link Control 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_LINKSTS2 0x32 /* Link Status 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_SLOTCAP2 0x34 /* Slot Capability 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_SLOTCTL2 0x38 /* Slot Control 2 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_SLOTSTS2 0x3A /* Slot Status 2 */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * PCI-Express Config Space size
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_CONF_HDR_SIZE 4096 /* PCIe configuration header size */
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * PCI-Express Capabilities Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_VER_1_0 0x1 /* PCI-E spec 1.0 */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_PCIECAP_VER_2_0 0x2 /* PCI-E spec 2.0 */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_VER_MASK 0xF /* Version Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_PCIE_DEV 0x00 /* PCI-E Endpont Device */
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango#define PCIE_PCIECAP_DEV_TYPE_PCI_DEV 0x10 /* "Leg PCI" Endpont Device */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_ROOT 0x40 /* Root Port of Root Complex */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_UP 0x50 /* Upstream Port of Switch */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_DOWN 0x60 /* Downstream Port of Switch */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_PCIE2PCI 0x70 /* PCI-E to PCI Bridge */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_PCI2PCIE 0x80 /* PCI to PCI-E Bridge */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae#define PCIE_PCIECAP_DEV_TYPE_RC_IEP 0x90 /* RootComplex Integrated Dev */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae#define PCIE_PCIECAP_DEV_TYPE_RC_EC 0xA0 /* RootComplex Evt Collector */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_DEV_TYPE_MASK 0xF0 /* Device/Port Type Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_PCIECAP_SLOT_IMPL 0x100 /* Slot Impl vs Integrated */
3221df98598173bea3b143712532cdd09f4fbd0fKrishna Elango#define PCIE_PCIECAP_INT_MSG_NUM 0x3E00 /* Interrupt Message Number */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Device Capabilities Register (4 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_128 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_256 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_512 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_1024 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_2048 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_4096 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_MAX_PAYLOAD_MASK 0x7 /* Max Payload Size Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PHTM_FUNC_NONE 0x00 /* No Function # bits used */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PHTM_FUNC_ONE 0x08 /* First most sig. bit used */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PHTM_FUNC_TWO 0x10 /* First 2 most sig bit used */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PHTM_FUNC_THREE 0x18 /* All 3 bits used */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PHTM_FUNC_MASK 0x18 /* Phantom Func Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EXT_TAG_5BIT 0x00 /* 5-Bit Tag Field Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EXT_TAG_8BIT 0x20 /* 8-Bit Tag Field Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EXT_TAG_MASK 0x20 /* Ext. Tag Field Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_MIN 0x000 /* < 64 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_64ns 0x040 /* 64 ns - 128 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_128ns 0x080 /* 128 ns - 256 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_256ns 0x0C0 /* 256 ns - 512 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_512ns 0x100 /* 512 ns - 1 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_1us 0x140 /* 1 us - 2 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_2us 0x180 /* 2 us - 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_MAX 0x1C0 /* > 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L0S_LAT_MASK 0x1C0 /* EP L0s Accetable Latency */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_MIN 0x000 /* < 1 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_1us 0x140 /* 1 us - 2 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_2us 0x180 /* 2 us - 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_4us 0x140 /* 4 us - 8 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_8us 0x180 /* 8 us - 16 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_16us 0x140 /* 16 us - 32 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_32us 0x180 /* 32 us - 64 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_MAX 0x1C0 /* > 64 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_EP_L1_LAT_MASK 0x700 /* EP L1 Accetable Latency */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_ATTN_BUTTON 0x1000 /* Attention Button Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_ATTN_INDICATOR 0x2000 /* Attn Indicator Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PWR_INDICATOR 0x4000 /* Power Indicator Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_DEVCAP_ROLE_BASED_ERR_REP 0x8000 /* Role Based Error Reporting */
337fc9e235877b459e389f54daf9833bbc645439anish
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_VAL_SHIFT 18 /* Power Limit Value Shift */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_VAL_MASK 0xFF /* Power Limit Value Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_SCL_1_BY_1 0x0000000 /* 1x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_SCL_1_BY_10 0x4000000 /* 0.1x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_SCL_1_BY_100 0x8000000 /* 0.01x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_SCL_1_BY_1000 0xC000000 /* 0.001x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCAP_PLMT_SCL_MASK 0xC000000 /* Power Limit Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Device Control Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_CE_REPORTING_EN 0x1 /* Correctable Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_NFE_REPORTING_EN 0x2 /* Non-Fatal Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_FE_REPORTING_EN 0x4 /* Fatal Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_UR_REPORTING_EN 0x8 /* Unsupported Request Enable */
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_ERR_MASK 0xF /* All of the above bits */
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_RO_EN 0x10 /* Enable Relaxed Ordering */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_128 0x00
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_256 0x20
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_512 0x40
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_1024 0x60
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_2048 0x80
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_4096 0xA0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_PAYLOAD_MASK 0xE0 /* Max_Payload_Size */
0114761d17f41c0b83189e4bf95e6b789e7ba99eAlan Adamson, SD OSSD#define PCIE_DEVCTL_MAX_PAYLOAD_SHIFT 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_EXT_TAG_FIELD_EN 0x100 /* Extended Tag Field Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_PHTM_FUNC_EN 0x200 /* Phantom Functions Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_AUX_POWER_PM_EN 0x400 /* Auxiliary Power PM Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_ENABLE_NO_SNOOP 0x800 /* Enable No Snoop */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_128 0x0000
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_256 0x1000
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_512 0x2000
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_1024 0x3000
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_2048 0x4000
95ad88f0c773d4a7dbe017b66e02eb6e9a0511c6raghuram#define PCIE_DEVCTL_MAX_READ_REQ_4096 0x5000
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVCTL_MAX_READ_REQ_MASK 0x7000 /* Max_Read_Request_Size */
0114761d17f41c0b83189e4bf95e6b789e7ba99eAlan Adamson, SD OSSD#define PCIE_DEVCTL_MAX_READ_REQ_SHIFT 0xC
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Device Status Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_CE_DETECTED 0x1 /* Correctable Error Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_NFE_DETECTED 0x2 /* Non Fatal Error Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_FE_DETECTED 0x4 /* Fatal Error Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_UR_DETECTED 0x8 /* Unsupported Req Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_AUX_POWER 0x10 /* AUX Power Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_DEVSTS_TRANS_PENDING 0x20 /* Transactions Pending */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Link Capability Register (4 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_SPEED_2_5 0x1 /* 2.5 Gb/s Speed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_SPEED_MASK 0xF /* Maximum Link Speed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X1 0x010
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X2 0x020
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X4 0x040
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X8 0x080
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X12 0x0C0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X16 0x100
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_X32 0x200
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_MAX_WIDTH_MASK 0x3f0 /* Maximum Link Width */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_ASPM_SUP_L0S 0x400 /* L0s Entry Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_ASPM_SUP_L0S_L1 0xC00 /* L0s abd L1 Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_ASPM_SUP_MASK 0xC00 /* ASPM Support */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_MIN 0x0000 /* < 64 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_64ns 0x1000 /* 64 ns - 128 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_128ns 0x2000 /* 128 ns - 256 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_256ns 0x3000 /* 256 ns - 512 ns */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_512ns 0x4000 /* 512 ns - 1 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_1us 0x5000 /* 1 us - 2 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_2us 0x6000 /* 2 us - 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_MAX 0x7000 /* > 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L0S_EXIT_LAT_MASK 0x7000 /* L0s Exit Latency */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_MIN 0x00000 /* < 1 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_1us 0x08000 /* 1 us - 2 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_2us 0x10000 /* 2 us - 4 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_4us 0x18000 /* 4 us - 8 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_8us 0x20000 /* 8 us - 16 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_16us 0x28000 /* 16 us - 32 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_32us 0x30000 /* 32 us - 64 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_MAX 0x38000 /* > 64 us */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCAP_L1_EXIT_LAT_MASK 0x38000 /* L1 Exit Latency */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
70025d765b044c6d8594bb965a2247a61e991a99johnny/* PCIe v1.1 spec based */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_LINKCAP_DLL_ACTIVE_REP_CAPABLE 0x100000 /* DLL Active */
70025d765b044c6d8594bb965a2247a61e991a99johnny /* Capable bit */
70025d765b044c6d8594bb965a2247a61e991a99johnny
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango#define PCIE_LINKCAP_PORT_NUMBER 0xFF000000 /* Port Number */
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango#define PCIE_LINKCAP_PORT_NUMBER_SHIFT 24 /* Port Number Shift */
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango#define PCIE_LINKCAP_PORT_NUMBER_MASK 0xFF /* Port Number Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Link Control Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_ASPM_CTL_DIS 0x0 /* ASPM Disable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_ASPM_CTL_L0S 0x1 /* ASPM L0s only */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_ASPM_CTL_L1 0x2 /* ASPM L1 only */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_ASPM_CTL_L0S_L1 0x3 /* ASPM L0s and L1 only */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_ASPM_CTL_MASK 0x3 /* ASPM Control */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_RCB_64_BYTE 0x0 /* 64 Byte */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_RCB_128_BYTE 0x8 /* 128 Byte */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_RCB_MASK 0x8 /* Read Completion Boundary */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_LINK_DISABLE 0x10 /* Link Disable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_RETRAIN_LINK 0x20 /* Retrain Link */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_COMMON_CLK_CFG 0x40 /* Common Clock Configuration */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKCTL_EXT_SYNCH 0x80 /* Extended Synch */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Link Status Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_SPEED_2_5 0x1 /* Link Speed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_SPEED_MASK 0xF /* Link Speed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X1 0x010
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X2 0x020
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X4 0x040
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X8 0x080
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X12 0x0C0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X16 0x100
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_X32 0x200
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_NEG_WIDTH_MASK 0x3F0 /* Negotiated Link Width */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_TRAINING_ERROR 0x400 /* Training Error */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_LINK_TRAINING 0x800 /* Link Training */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_LINKSTS_SLOT_CLK_CFG 0x1000 /* Slot Clock Configuration */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f94c602698937f2fc025056c894e5a769f39d8fejj/* PCIe v1.1 spec based */
f94c602698937f2fc025056c894e5a769f39d8fejj#define PCIE_LINKSTS_DLL_LINK_ACTIVE 0x2000 /* DLL Link Active */
f94c602698937f2fc025056c894e5a769f39d8fejj
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Slot Capability Register (4 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_ATTN_BUTTON 0x1 /* Attention Button Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_POWER_CONTROLLER 0x2 /* Power Controller Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_MRL_SENSOR 0x4 /* MRL Sensor Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_ATTN_INDICATOR 0x8 /* Attn Indicator Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PWR_INDICATOR 0x10 /* Power Indicator Present */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_HP_SURPRISE 0x20 /* Hot-Plug Surprise */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_HP_CAPABLE 0x40 /* Hot-Plug Capable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_VAL_SHIFT 7 /* Slot Pwr Limit Value Shift */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_VAL_MASK 0xFF /* Slot Pwr Limit Value */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_SCL_1_BY_1 0x00000 /* 1x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_SCL_1_BY_10 0x08000 /* 0.1x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_SCL_1_BY_100 0x10000 /* 0.01x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_SCL_1_BY_1000 0x18000 /* 0.001x Scale */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PLMT_SCL_MASK 0x18000 /* Slot Power Limit Scale */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCAP_EMI_LOCK_PRESENT 0x20000 /* EMI Lock Present */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCAP_NO_CMD_COMP_SUPP 0x40000 /* No Command Comp. Supported */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PHY_SLOT_NUM_SHIFT 19 /* Physical Slot Num Shift */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCAP_PHY_SLOT_NUM_MASK 0x1FFF /* Physical Slot Num Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCAP_PHY_SLOT_NUM(reg) \
70025d765b044c6d8594bb965a2247a61e991a99johnny (((reg) >> PCIE_SLOTCAP_PHY_SLOT_NUM_SHIFT) & \
70025d765b044c6d8594bb965a2247a61e991a99johnny PCIE_SLOTCAP_PHY_SLOT_NUM_MASK)
70025d765b044c6d8594bb965a2247a61e991a99johnny
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Slot Control Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_ATTN_BTN_EN 0x1 /* Attn Button Pressed Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_PWR_FAULT_EN 0x2 /* Pwr Fault Detected Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_MRL_SENSOR_EN 0x4 /* MRL Sensor Changed Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_PRESENCE_CHANGE_EN 0x8 /* Presence Detect Changed En */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_CMD_INTR_EN 0x10 /* CMD Completed Interrupt En */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTCTL_HP_INTR_EN 0x20 /* Hot-Plug Interrupt Enable */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_PWR_CONTROL 0x0400 /* Power controller Control */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_EMI_LOCK_CONTROL 0x0800 /* EMI Lock control */
f94c602698937f2fc025056c894e5a769f39d8fejj#define PCIE_SLOTCTL_DLL_STATE_EN 0x1000 /* DLL State Changed En */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_ATTN_INDICATOR_MASK 0x00C0 /* Attn Indicator mask */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_PWR_INDICATOR_MASK 0x0300 /* Power Indicator mask */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_SLOTCTL_INTR_MASK 0x103f /* Supported intr mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
70025d765b044c6d8594bb965a2247a61e991a99johnny/* State values for the Power and Attention Indicators */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_INDICATOR_STATE_ON 0x1 /* indicator ON */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_INDICATOR_STATE_BLINK 0x2 /* indicator BLINK */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTCTL_INDICATOR_STATE_OFF 0x3 /* indicator OFF */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Macros to set/get the state of Power and Attention Indicators
70025d765b044c6d8594bb965a2247a61e991a99johnny * in the PCI Express Slot Control Register.
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define pcie_slotctl_pwr_indicator_get(reg) \
70025d765b044c6d8594bb965a2247a61e991a99johnny (((reg) & PCIE_SLOTCTL_PWR_INDICATOR_MASK) >> 8)
70025d765b044c6d8594bb965a2247a61e991a99johnny#define pcie_slotctl_attn_indicator_get(ctrl) \
70025d765b044c6d8594bb965a2247a61e991a99johnny (((ctrl) & PCIE_SLOTCTL_ATTN_INDICATOR_MASK) >> 6)
70025d765b044c6d8594bb965a2247a61e991a99johnny#define pcie_slotctl_attn_indicator_set(ctrl, v)\
70025d765b044c6d8594bb965a2247a61e991a99johnny (((ctrl) & ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK) | ((v) << 6))
70025d765b044c6d8594bb965a2247a61e991a99johnny#define pcie_slotctl_pwr_indicator_set(ctrl, v)\
70025d765b044c6d8594bb965a2247a61e991a99johnny (((ctrl) & ~PCIE_SLOTCTL_PWR_INDICATOR_MASK) | ((v) << 8))
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Slot Status register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_ATTN_BTN_PRESSED 0x1 /* Attention Button Pressed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_PWR_FAULT_DETECTED 0x2 /* Power Fault Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_MRL_SENSOR_CHANGED 0x4 /* MRL Sensor Changed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_PRESENCE_CHANGED 0x8 /* Presence Detect Changed */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_COMMAND_COMPLETED 0x10 /* Command Completed */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTSTS_MRL_SENSOR_OPEN 0x20 /* MRL Sensor Open */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_SLOTSTS_PRESENCE_DETECTED 0x40 /* Card Present in slot */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTSTS_EMI_LOCK_SET 0x0080 /* EMI Lock set */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_SLOTSTS_DLL_STATE_CHANGED 0x0100 /* DLL State Changed */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_SLOTSTS_STATUS_EVENTS 0x11f /* Supported events */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Root Control Register (2 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTCTL_SYS_ERR_ON_CE_EN 0x1 /* Sys Err on Cor Err Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTCTL_SYS_ERR_ON_NFE_EN 0x2 /* Sys Err on NF Err Enable */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_ROOTCTL_SYS_ERR_ON_FE_EN 0x4 /* Sys Err on Fatal Err En */
70025d765b044c6d8594bb965a2247a61e991a99johnny#define PCIE_ROOTCTL_PME_INTERRUPT_EN 0x8 /* PME Interrupt Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Root Status Register (4 bytes)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTSTS_PME_REQ_ID_SHIFT 0 /* PME Requestor ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTSTS_PME_REQ_ID_MASK 0xFFFF /* PME Requestor ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTSTS_PME_STATUS 0x10000 /* PME Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_ROOTSTS_PME_PENDING 0x20000 /* PME Pending */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
269473047d747f7815af570197e4ef7322d3632cEvan Yan/*
269473047d747f7815af570197e4ef7322d3632cEvan Yan * Device Capabilities 2 Register (4 bytes)
269473047d747f7815af570197e4ef7322d3632cEvan Yan */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_COM_TO_RANGE_MASK 0xF
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_COM_TO_DISABLE 0x10
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_ARI_FORWARD 0x20
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_ATOMICOP_ROUTING 0x40
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_32_ATOMICOP_COMPL 0x80
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_64_ATOMICOP_COMPL 0x100
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_128_CAS_COMPL 0x200
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_NO_RO_PR_PR_PASS 0x400
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_LTR_MECH 0x800
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_TPH_COMP_SHIFT 12
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_TPH_COMP_MASK 0x3
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_EXT_FMT_FIELD 0x100000
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_END_END_TLP_PREFIX 0x200000
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_MAX_END_END_SHIFT 22
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCAP2_MAX_END_END_MASK 0x3
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan/*
269473047d747f7815af570197e4ef7322d3632cEvan Yan * Device Control 2 Register (2 bytes)
269473047d747f7815af570197e4ef7322d3632cEvan Yan */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_0 0x0
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_1 0x1
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_2 0x2
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_3 0x5
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_4 0x6
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_5 0x9
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_6 0xa
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_7 0xd
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_RANGE_8 0xe
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_COM_TO_DISABLE 0x10
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_ARI_FORWARD_EN 0x20
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_ATOMICOP_REQ_EN 0x40
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_ATOMICOP_EGRS_BLK 0x80
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_IDO_REQ_EN 0x100
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_IDO_COMPL_EN 0x200
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_LTR_MECH_EN 0x400
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_DEVCTL2_END_END_TLP_PREFIX 0x8000
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * PCI-Express Enhanced Capabilities Link Entry Bit Offsets
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP 0x100 /* Base Address of Ext Cap */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_ID_SHIFT 0 /* PCI-e Ext Cap ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_ID_MASK 0xFFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_VER_SHIFT 16 /* PCI-e Ext Cap Ver */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_VER_MASK 0xF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_NEXT_PTR_SHIFT 20 /* PCI-e Ext Cap Next Ptr */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_NEXT_PTR_MASK 0xFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_NEXT_PTR_NULL 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * PCI-Express Enhanced Capability Identifier Values
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_ID_AER 0x1 /* Advanced Error Handling */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_VC 0x2 /* Virtual Channel, no MFVC */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_ID_SER 0x3 /* Serial Number */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_EXT_CAP_ID_PWR_BUDGET 0x4 /* Power Budgeting */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_RC_LINK_DECL 0x5 /* RC Link Declaration */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_RC_INT_LINKCTRL 0x6 /* RC Internal Link Control */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_RC_EVNT_CEA 0x7 /* RC Event Collector */
337fc9e235877b459e389f54daf9833bbc645439anish /* Endpoint Association */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_MFVC 0x8 /* Multi-func Virtual Channel */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_VC_WITH_MFVC 0x9 /* Virtual Channel w/ MFVC */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_RCRB 0xA /* Root Complex Register Blck */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_VS 0xB /* Vendor Spec Extended Cap */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_CAC 0xC /* Config Access Correlation */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_ACS 0xD /* Access Control Services */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_ARI 0xE /* Alternative Routing ID */
337fc9e235877b459e389f54daf9833bbc645439anish#define PCIE_EXT_CAP_ID_ATS 0xF /* Address Translation Svcs */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * PCI-Express Advanced Error Reporting Extended Capability Offsets
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CAP 0x0 /* Enhanced Capability Header */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_STS 0x4 /* Uncorrectable Error Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_MASK 0x8 /* Uncorrectable Error Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_SERV 0xc /* Uncor Error Severity */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_STS 0x10 /* Correctable Error Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_MASK 0x14 /* Correctable Error Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL 0x18 /* AER Capability & Control */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_HDR_LOG 0x1c /* Header Log */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Root Ports Only */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_CMD 0x2c /* Root Error Command */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS 0x30 /* Root Error Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_SRC_ID 0x34 /* Error Source ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_ERR_SRC_ID 0x36 /* Error Source ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Bridges Only */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_STS 0x2c /* Secondary UCE Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_MASK 0x30 /* Secondary UCE Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_SERV 0x34 /* Secondary UCE Severity */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SCTL 0x38 /* Secondary Cap & Ctl */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SHDR_LOG 0x3c /* Secondary Header Log */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Uncorrectable Error Status/Mask/Severity Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_UCE_TRAINING 0x1 /* Training Error Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_DLP 0x10 /* Data Link Protocol Error */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_UCE_SD 0x20 /* Link Surprise down */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_PTLP 0x1000 /* Poisoned TLP Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_FCP 0x2000 /* Flow Control Protocol Sts */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_TO 0x4000 /* Completion Timeout Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_CA 0x8000 /* Completer Abort Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_UC 0x10000 /* Unexpected Completion Sts */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_RO 0x20000 /* Receiver Overflow Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_MTLP 0x40000 /* Malformed TLP Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_ECRC 0x80000 /* ECRC Error Status */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_UCE_UR 0x100000 /* Unsupported Req */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_UCE_BITS (PCIE_AER_UCE_TRAINING | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_UCE_DLP | PCIE_AER_UCE_SD | PCIE_AER_UCE_PTLP | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_UCE_FCP | PCIE_AER_UCE_TO | PCIE_AER_UCE_CA | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_UCE_UC | PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_UCE_ECRC | PCIE_AER_UCE_UR)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_UCE_LOG_BITS (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_CA | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_UCE_UC | PCIE_AER_UCE_MTLP | PCIE_AER_UCE_ECRC | PCIE_AER_UCE_UR)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Correctable Error Status/Mask Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_RECEIVER_ERR 0x1 /* Receiver Error Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_BAD_TLP 0x40 /* Bad TLP Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_BAD_DLLP 0x80 /* Bad DLLP Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_REPLAY_ROLLOVER 0x100 /* REPLAY_NUM Rollover Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_REPLAY_TO 0x1000 /* Replay Timer Timeout Sts */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_CE_AD_NFE 0x2000 /* Advisory Non-Fatal Status */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CE_BITS (PCIE_AER_CE_RECEIVER_ERR | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_CE_BAD_TLP | PCIE_AER_CE_BAD_DLLP | PCIE_AER_CE_REPLAY_ROLLOVER | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_CE_REPLAY_TO)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Capability & Control
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL_FST_ERR_PTR_MASK 0x1F /* First Error Pointer */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL_ECRC_GEN_CAP 0x20 /* ECRC Generation Capable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL_ECRC_GEN_ENA 0x40 /* ECRC Generation Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL_ECRC_CHECK_CAP 0x80 /* ECRC Check Capable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_CTL_ECRC_CHECK_ENA 0x100 /* ECRC Check Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Root Command Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_CMD_CE_REP_EN 0x1 /* Correctable Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_CMD_NFE_REP_EN 0x2 /* Non-Fatal Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_CMD_FE_REP_EN 0x4 /* Fatal Error Enable */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Root Error Status Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_CE_RCVD 0x1 /* ERR_COR Received */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_MUL_CE_RCVD 0x2 /* Multiple ERR_COR Received */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_FE_NFE_RCVD 0x4 /* FATAL/NON-FATAL Received */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_MUL_FE_NFE_RCVD 0x8 /* Multiple ERR_F/NF Received */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_FIRST_UC_FATAL 0x10 /* First Uncorrectable Fatal */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_NFE_MSGS_RCVD 0x20 /* Non-Fatal Error Msgs Rcvd */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_FE_MSGS_RCVD 0x40 /* Fatal Error Messages Rcvd */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_MSG_NUM_SHIFT 27 /* Offset of Intr Msg Number */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_RE_STS_MSG_NUM_MASK 0x1F /* Intr Msg Number Mask */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Error Source Identification Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_ERR_SRC_ID_CE_SHIFT 0 /* ERR_COR Source ID */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_ERR_SRC_ID_CE_MASK 0xFFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_ERR_SRC_ID_UE_SHIFT 16 /* ERR_FATAL/NONFATAL Src ID */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae#define PCIE_AER_ERR_SRC_ID_UE_MASK 0xFFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Secondary Uncorrectable Error Register
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_TA_ON_SC 0x1 /* Target Abort on Split Comp */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_MA_ON_SC 0x2 /* Master Abort on Split Comp */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_RCVD_TA 0x4 /* Received Target Abort */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_RCVD_MA 0x8 /* Received Master Abort */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_USC_ERR 0x20 /* Unexpected Split Comp Err */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_USC_MSG_DATA_ERR 0x40 /* USC Message Data Error */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_UC_DATA_ERR 0x80 /* Uncorrectable Data Error */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_UC_ATTR_ERR 0x100 /* UC Attribute Err */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_UC_ADDR_ERR 0x200 /* Uncorrectable Address Err */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_TIMER_EXPIRED 0x400 /* Delayed xtion discard */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_PERR_ASSERT 0x800 /* PERR Assertion Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_SERR_ASSERT 0x1000 /* SERR Assertion Detected */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_INTERNAL_ERR 0x2000 /* Internal Bridge Err Detect */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_HDR_CMD_LWR_MASK 0xF /* Lower Command Mask */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_HDR_CMD_LWR_SHIFT 4 /* Lower Command Shift */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_HDR_CMD_UP_MASK 0xF /* Upper Command Mask */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_HDR_CMD_UP_SHIFT 8 /* Upper Command Shift */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_HDR_ADDR_SHIFT 32 /* Upper Command Shift */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SUCE_BITS (PCIE_AER_SUCE_TA_ON_SC | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_MA_ON_SC | PCIE_AER_SUCE_RCVD_TA | PCIE_AER_SUCE_RCVD_MA | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_USC_ERR | PCIE_AER_SUCE_USC_MSG_DATA_ERR | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_UC_DATA_ERR | PCIE_AER_SUCE_UC_ATTR_ERR | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_UC_ADDR_ERR | PCIE_AER_SUCE_TIMER_EXPIRED | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_PERR_ASSERT | PCIE_AER_SUCE_SERR_ASSERT | \
f8d2de6bd2421da1926f3daa456d161670decdf7jchu PCIE_AER_SUCE_INTERNAL_ERR)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_AER_SUCE_LOG_BITS (PCIE_AER_SUCE_TA_ON_SC | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_SUCE_MA_ON_SC | PCIE_AER_SUCE_RCVD_TA | PCIE_AER_SUCE_RCVD_MA | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_SUCE_USC_ERR | PCIE_AER_SUCE_USC_MSG_DATA_ERR | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_SUCE_UC_DATA_ERR | PCIE_AER_SUCE_UC_ATTR_ERR | \
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet PCIE_AER_SUCE_UC_ADDR_ERR | PCIE_AER_SUCE_PERR_ASSERT)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Secondary Capability & Control
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SCTL_FST_ERR_PTR_MASK 0x1F /* First Error Pointer */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * AER Secondary Headers
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The Secondary Header Logs is 4 DW long.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The first 2 DW are split into 3 sections
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * o Transaction Attribute
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * o Transaction Command Lower
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * o Transaction Command Higher
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The last 2 DW is the Transaction Address
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SHDR_LOG_ATTR_MASK 0xFFFFFFFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SHDR_LOG_CMD_LOW_MASK 0xF000000000
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SHDR_LOG_CMD_HIGH_MASK 0xF0000000000
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_AER_SHDR_LOG_ADDR_MASK 0xFFFFFFFFFFFFFFFF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda/*
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda * PCI-Express Device Serial Number Capability Offsets.
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda */
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda#define PCIE_SER_CAP 0x0 /* Enhanced Capability Header */
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda#define PCIE_SER_SID_LOWER_DW 0x4 /* Lower 32-bit Serial Number */
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda#define PCIE_SER_SID_UPPER_DW 0x8 /* Upper 32-bit Serial Number */
665a7fca9fb82b4c029eb6763aefcc9bc563a486govinda
269473047d747f7815af570197e4ef7322d3632cEvan Yan/*
269473047d747f7815af570197e4ef7322d3632cEvan Yan * ARI Capability Offsets
269473047d747f7815af570197e4ef7322d3632cEvan Yan */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_HDR 0x0 /* Enhanced Capability Header */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CAP 0x4 /* ARI Capability Register */
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CTL 0x6 /* ARI Control Register */
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CAP_MFVC_FUNC_GRP 0x01
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CAP_ASC_FUNC_GRP 0x02
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CAP_NEXT_FUNC_SHIFT 8
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CAP_NEXT_FUNC_MASK 0xffff
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CTRL_MFVC_FUNC_GRP 0x01
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CTRL_ASC_FUNC_GRP 0x02
269473047d747f7815af570197e4ef7322d3632cEvan Yan
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CTRL_FUNC_GRP_SHIFT 4
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_ARI_CTRL_FUNC_GRP_MASK 0x7
269473047d747f7815af570197e4ef7322d3632cEvan Yan
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * PCI-E Common TLP Header Fields
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_FMT_3DW 0x00
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_FMT_4DW 0x20
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_FMT_3DW_DATA 0x40
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_FMT_4DW_DATA 0x60
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_MEM 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_MEMLK 0x1
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_TYPE_IO 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_CFG0 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_CFG1 0x5
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_TYPE_MSG 0x10
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_CPL 0xA
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_CPLLK 0xB
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_TYPE_MSI 0x18
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRD3 (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_MEM)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRD4 (PCIE_TLP_FMT_4DW | PCIE_TLP_TYPE_MEM)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRDLK3 (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_MEMLK)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRDLK4 (PCIE_TLP_FMT_4DW | PCIE_TLP_TYPE_MEMLK)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRDWR3 (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_MEM)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MRDWR4 (PCIE_TLP_FMT_4DW_DATA | PCIE_TLP_TYPE_MEM)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_IORD (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_IO)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_IOWR (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_IO)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CFGRD0 (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_CFG0)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CFGWR0 (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_CFG0)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CFGRD1 (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_CFG1)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CFGWR1 (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_CFG1)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_MSG (PCIE_TLP_FMT_4DW | PCIE_TLP_TYPE_MSG)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#define PCIE_TLP_MSGD (PCIE_TLP_FMT_4DW_DATA | PCIE_TLP_TYPE_MSG)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CPL (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_CPL)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CPLD (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_CPL)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CPLLK (PCIE_TLP_FMT_3DW | PCIE_TLP_TYPE_CPLLK)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_CPLDLK (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_CPLLK)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MSI32 (PCIE_TLP_FMT_3DW_DATA | PCIE_TLP_TYPE_MSI)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_TLP_MSI64 (PCIE_TLP_FMT_4DW_DATA | PCIE_TLP_TYPE_MSI)
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef uint16_t pcie_req_id_t;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_REQ_ID_BUS_SHIFT 8
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_REQ_ID_BUS_MASK 0xFF00
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_REQ_ID_DEV_SHIFT 3
c85864d8472aaccb47ceb468ebd9b3a85b66d161Krishna Elango#define PCIE_REQ_ID_DEV_MASK 0x00F8
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_REQ_ID_FUNC_SHIFT 0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_REQ_ID_FUNC_MASK 0x0007
269473047d747f7815af570197e4ef7322d3632cEvan Yan#define PCIE_REQ_ID_ARI_FUNC_MASK 0x00FF
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
bf8fc2340620695a402331e5da7c7db43264174det#define PCIE_CPL_STS_SUCCESS 0
bf8fc2340620695a402331e5da7c7db43264174det#define PCIE_CPL_STS_UR 1
bf8fc2340620695a402331e5da7c7db43264174det#define PCIE_CPL_STS_CRS 2
bf8fc2340620695a402331e5da7c7db43264174det#define PCIE_CPL_STS_CA 4
bf8fc2340620695a402331e5da7c7db43264174det
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#if defined(_BIT_FIELDS_LTOH)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet/*
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet * PCI Express little-endian common TLP header format
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_tlp_hdr {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t len :10,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd3 :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet attr :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet ep :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet td :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd2 :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tc :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd1 :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet type :5,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet fmt :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :1;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_tlp_hdr_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_mem64 {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t fbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t addr1;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rsvd0 :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet addr0 :30;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_mem64_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_memio32 {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t fbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rsvd0 :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet addr0 :30;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_memio32_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_cfg {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t fbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rsvd1 :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet reg :6,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet extreg :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet func :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet dev :5,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet bus :8;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_cfg_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_cpl {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t bc :12,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet bcm :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet status :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet cid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t laddr :7,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_cpl_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * PCI-Express Message Request Header
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef struct pcie_msg {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t msg_code:8, /* DW1 */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rid :16;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t unused[2]; /* DW 2 & 3 */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_msg_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#elif defined(_BIT_FIELDS_HTOL)
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet/*
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet * PCI Express big-endian common TLP header format
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_tlp_hdr {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rsvd0 :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet fmt :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet type :5,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd1 :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tc :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd2 :4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu td :1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu ep :1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu attr :2,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd3 :2,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu len :10;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_tlp_hdr_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_mem64 {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rid :16,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet fbe :4;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t addr1;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t addr0 :30,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :2;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_mem64_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_memio32 {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rid :16,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet fbe :4;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t addr0 :30,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :2;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_memio32_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_cfg {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rid :16,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet lbe :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet fbe :4;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t bus :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet dev :5,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet func :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet extreg :4,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet reg :6,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd1 :2;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_cfg_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_cpl {
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t cid :16,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet status :3,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet bcm :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet bc :12;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet uint32_t rid :16,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet tag :8,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet rsvd0 :1,
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet laddr :7;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet} pcie_cpl_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet/*
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet * PCI-Express Message Request Header
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet */
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreettypedef struct pcie_msg {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t rid :16, /* DW1 */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu tag :8,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu msg_code:8;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t unused[2]; /* DW 2 & 3 */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu} pcie_msg_t;
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#else
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#error "bit field not defined"
00d0963faf2e861a4aef6b1bf28f99a5b2b20755dilpreet#endif
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_MSG_CODE_ERR_COR 0x30
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_MSG_CODE_ERR_NONFATAL 0x31
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PCIE_MSG_CODE_ERR_FATAL 0x33
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifdef __cplusplus
f8d2de6bd2421da1926f3daa456d161670decdf7jchu}
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif /* _SYS_PCIE_H */