/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCIE_H
#define _SYS_PCIE_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Express capability registers in PCI configuration space relative to
* the PCI Express Capability structure.
*/
/*
* PCI-Express Config Space size
*/
/*
* PCI-Express Capabilities Register (2 bytes)
*/
/*
* Device Capabilities Register (4 bytes)
*/
/*
* Device Control Register (2 bytes)
*/
/*
* Device Status Register (2 bytes)
*/
/*
* Link Capability Register (4 bytes)
*/
/* PCIe v1.1 spec based */
/* Capable bit */
/*
* Link Control Register (2 bytes)
*/
/*
* Link Status Register (2 bytes)
*/
/* PCIe v1.1 spec based */
/*
* Slot Capability Register (4 bytes)
*/
(((reg) >> PCIE_SLOTCAP_PHY_SLOT_NUM_SHIFT) & \
/*
* Slot Control Register (2 bytes)
*/
/* State values for the Power and Attention Indicators */
/*
* in the PCI Express Slot Control Register.
*/
/*
* Slot Status register (2 bytes)
*/
/*
* Root Control Register (2 bytes)
*/
/*
* Root Status Register (4 bytes)
*/
/*
* Device Capabilities 2 Register (4 bytes)
*/
/*
* Device Control 2 Register (2 bytes)
*/
/*
* PCI-Express Enhanced Capabilities Link Entry Bit Offsets
*/
/*
* PCI-Express Enhanced Capability Identifier Values
*/
/* Endpoint Association */
/*
* PCI-Express Advanced Error Reporting Extended Capability Offsets
*/
/* Root Ports Only */
/* Bridges Only */
/*
*/
/*
*/
/*
* AER Capability & Control
*/
/*
* AER Root Command Register
*/
/*
* AER Root Error Status Register
*/
/*
* AER Error Source Identification Register
*/
/*
* AER Secondary Uncorrectable Error Register
*/
/*
* AER Secondary Capability & Control
*/
/*
* AER Secondary Headers
* The Secondary Header Logs is 4 DW long.
* The first 2 DW are split into 3 sections
* o Transaction Attribute
* o Transaction Command Lower
* o Transaction Command Higher
* The last 2 DW is the Transaction Address
*/
/*
* PCI-Express Device Serial Number Capability Offsets.
*/
/*
* ARI Capability Offsets
*/
/*
* PCI-E Common TLP Header Fields
*/
#define PCIE_REQ_ID_FUNC_SHIFT 0
#define PCIE_CPL_STS_SUCCESS 0
#if defined(_BIT_FIELDS_LTOH)
/*
* PCI Express little-endian common TLP header format
*/
typedef struct pcie_tlp_hdr {
typedef struct pcie_mem64 {
} pcie_mem64_t;
typedef struct pcie_memio32 {
typedef struct pcie_cfg {
} pcie_cfg_t;
typedef struct pcie_cpl {
} pcie_cpl_t;
/*
* PCI-Express Message Request Header
*/
typedef struct pcie_msg {
} pcie_msg_t;
#elif defined(_BIT_FIELDS_HTOL)
/*
* PCI Express big-endian common TLP header format
*/
typedef struct pcie_tlp_hdr {
typedef struct pcie_mem64 {
} pcie_mem64_t;
typedef struct pcie_memio32 {
typedef struct pcie_cfg {
} pcie_cfg_t;
typedef struct pcie_cpl {
} pcie_cpl_t;
/*
* PCI-Express Message Request Header
*/
typedef struct pcie_msg {
} pcie_msg_t;
#else
#error "bit field not defined"
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCIE_H */