/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Intel 82365SL device and register definitions
*/
#ifndef _PCIC_REG_H
#define _PCIC_REG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* global information
*/
/*
* per socket information
*/
/* number of windows per chip */
/* number of windows per socket */
/*
* socket selection registers
*
* the PCIC allows up to 8 sockets per system
* this is done by having two sockets per chip and up to 4 chips per
* system. There can be up to 4 sockets (2 PCIC chips) per I/O address.
* There are two possible I/O address (index register) values.
* socket# I/O address value to write to index register
* 0 INDEX_REG0 BASE0 + SOCKET_0 + register offset
* 1 INDEX_REG0 BASE0 + SOCKET_1 + register offset
* 2 INDEX_REG0 BASE1 + SOCKET_0 + register offset
* 3 INDEX_REG0 BASE1 + SOCKET_1 + register offset
* next 4 are based off of INDEX_REG1
*/
/*
* per socket register
* these are accessed by writing the offset value into the
* index register and adding the appropriate base offset and socket offset
* the register is then present in the data register.
*/
/* General Registers */
/* Interrupt Registers */
/* I/O Registers */
/* Memory Registers */
/* window 0 */
/* window 1 */
/* Cirrus Logic specific registers */
/*
* Cirrus Logic PCI-PCMCIA adapters extension register indicies
*/
/* the 6832 is mapped into different offsets for extension regs */
/*
* Cirrus Logic PCI-PCMCIA PCIC_CLEXT_EXT_CTL_1 reg bit definitions
*/
/*
* Cirrus Logic PCI-PCMCIA PCIC_MISC_CTL_2 reg bit definitions
*/
/*
* Cirrus Logic PCI-PCMCIA PCIC_CLEXT_MISC_CTL_3 reg bit definitions
*/
/*
* Intel 82092-AA reg and bit definitions
*/
/*
* identification and revision register
*/
/*
* interface status register bit definitions
*/
/*
* memory register definitions
*/
/* interrupt register definitions */
/* card status change register definitions */
/* card status change interrupt register definitions */
/* card detect change register */
/* misc control 1 */
/* global control registers definitions */
/* misc control 2 */
/* chip info register (Cirrus) definitions */
/* Vadem unique registers */
/* Vadem DMA Register */
/* Vadem identification register */
/* Vadem Voltage Select */
/* Vadem Control Register */
/* Vadem Extended Mode Register A */
/* Ricoh Specific Registers */
/* O2 Micro Specific registers */
/* Texas Instruments specific Registers */
/* for PCI1420 chip */
/* for PCI1225 chip */
/* for PCI1221 and PCI1225 chips */
/* for PCI1221 and PCI1225 chips */
/* for Toshiba chips */
/* for Ricoh chips */
/* for o2micro */
/* */
/* SMC 34C90 specific registers */
/* available interrupts and interrupt mask */
/* page size used for window mapping and memory resource page size */
/* used in I/O window mapping */
/* CardBus (Yenta) specific values */
/* Register offsets (these are 32 bit registers). */
/* TI1420 */
/* Cardbus registers in 02 0Z6912. */
/* Register bit definitions. */
#define BYTE_0(x) (x)
#ifdef __cplusplus
}
#endif
#endif /* _PCIC_REG_H */