pci.h revision 9c75c6bf17b72bb057d7a8879feba77ece65241a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCI_H
#define _SYS_PCI_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Configuration Header offsets
*/
/*
* Header type 0 offsets
*/
/*
* PCI to PCI bridge configuration space header format
*/
#define PCI_BCNF_LATENCY_TIMER 0x1b
#define PCI_BCNF_IO_BASE_LOW 0x1c
#define PCI_BCNF_IO_LIMIT_LOW 0x1d
#define PCI_BCNF_SEC_STATUS 0x1e
#define PCI_BCNF_MEM_BASE 0x20
#define PCI_BCNF_MEM_LIMIT 0x22
#define PCI_BCNF_PF_BASE_LOW 0x24
#define PCI_BCNF_PF_LIMIT_LOW 0x26
#define PCI_BCNF_PF_BASE_HIGH 0x28
#define PCI_BCNF_PF_LIMIT_HIGH 0x2c
#define PCI_BCNF_IO_BASE_HI 0x30
#define PCI_BCNF_IO_LIMIT_HI 0x32
#define PCI_BCNF_CAP_PTR 0x34
#define PCI_BCNF_ROM 0x38
#define PCI_BCNF_ILINE 0x3c
#define PCI_BCNF_IPIN 0x3d
#define PCI_BCNF_BCNTRL 0x3e
#define PCI_BCNF_BASE_NUM 0x2
/*
* PCI to PCI bridge control register (0x3e) format
*/
#define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1
#define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2
#define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20
#define PCI_BCNF_BCNTRL_DTO_STAT 0x400
#define PCI_BCNF_IO_MASK 0xf0
#define PCI_BCNF_MEM_MASK 0xfff0
/*
* Header type 2 (Cardbus) offsets
*/
/*
* PCI command register bits
*/
#define PCI_COMM_SPEC_CYC 0x8
#define PCI_COMM_MEMWR_INVAL 0x10
#define PCI_COMM_PALETTE_SNOOP 0x20
#define PCI_COMM_PARITY_DETECT 0x40
#define PCI_COMM_WAIT_CYC_ENAB 0x80
#define PCI_COMM_SERR_ENABLE 0x100
#define PCI_COMM_BACK2BACK_ENAB 0x200
/*
* PCI Interrupt pin value
*/
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
/*
* PCI status register bits
*/
/*
* DEVSEL timing values
*/
#define PCI_STAT_DEVSELT_FAST 0x0000
#define PCI_STAT_DEVSELT_MEDIUM 0x0200
#define PCI_STAT_DEVSELT_SLOW 0x0400
/*
* BIST values
*/
#define PCI_BIST_SUPPORTED 0x80
#define PCI_BIST_GO 0x40
#define PCI_BIST_RESULT_M 0x0f
#define PCI_BIST_RESULT_OK 0x00
/*
* PCI class codes
*/
/*
* PCI Sub-class codes - base class 0x0 (no new devices should use this code).
*/
/*
* PCI Sub-class codes - base class 0x1 (mass storage controllers)
*/
/*
* programming interface for IDE (subclass 1)
*/
/*
* programming interface for ATA (subclass 5)
*/
/*
* PCI Sub-class codes - base class 0x2 (Network controllers)
*/
/*
* PCI Sub-class codes - base class 03 (display controllers)
*/
/*
* programming interface for display for display class (subclass 0) VGA ctrlrs
*/
/*
* PCI Sub-class codes - base class 0x4 (multi-media devices)
*/
/*
* PCI Sub-class codes - base class 0x5 (memory controllers)
*/
/*
* PCI Sub-class codes - base class 0x6 (Bridge devices)
*/
/*
* programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 09)
* Semi-transparent PCI-to-PCI bridge
*/
/* facing system processor */
/* facing system processor */
/*
* PCI Sub-class codes - base class 0x7 (communication devices)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x0 (Serial)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x3 (Modem)
*/
/*
* PCI Sub-class codes - base class 0x8
*/
/*
* Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x2 (timer)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
*/
/*
* PCI Sub-class codes - base class 0x9
*/
/*
* Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
*/
/*
* PCI Sub-class codes - base class 0xa
*/
/*
* PCI Sub-class codes - base class 0xb
*/
/*
* PCI Sub-class codes - base class 0xc (Serial Controllers)
*/
/*
* Programming interfaces for class 0xC / subclass 0x3 (USB controller)
*/
/*
* Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
*/
/*
* PCI Sub-class codes - base class 0xd (Wireless controllers)
*/
/*
* PCI Sub-class codes - base class 0xe (Intelligent I/O controllers)
*/
/*
* PCI Sub-class codes - base class 0xf (Satellite Communication controllers)
*/
/*
* PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
*/
/*
* PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
*/
/* time and freq test ctrlr */
/* PCI header decode */
/*
* Base register bit definitions.
*/
/*
* Capabilities linked list entry offsets
*/
/*
* Capability identifier values
*/
/*
* Capability next entry pointer values
*/
/*
* PCI power management (PM) capability entry offsets
*/
/*
* PM capabilities values - 2 bytes
*/
/*
*/
/*
* PM PMCSR PCI to PCI bridge support extension values - 1 byte
*/
/*
* PCI-X capability related definitions
*/
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability masks and shifts
*/
/*
* PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
*/
#define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */
/*
* PCI Message Signalled Interrupts: other interesting constants
*/
/*
* PCI Slot Id Capabilities, 2 bytes
*/
/* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
/*
* other interesting PCI constants
*/
/*
* This structure represents one entry of the 1275 "reg" property and
* "assigned-addresses" property for a PCI node. For the "reg" property, it
* may be one of an arbitrary length array for devices with multiple address
* windows. For the "assigned-addresses" property, it denotes an assigned
* physical address on the PCI bus. It may be one entry of the six entries
* for devices with multiple base registers.
*
* The physical address format is:
*
* Bit#: 33222222 22221111 11111100 00000000
* 10987654 32109876 54321098 76543210
*
* pci_phys_hi cell: np0000tt bbbbbbbb dddddfff rrrrrrrr
* pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_phys_low cell: llllllll llllllll llllllll llllllll
*
* n is 0 if the address is relocatable, 1 otherwise
* p is 1 if the addressable region is "prefetchable", 0 otherwise
* t is 1 if the address range is aliased
* tt is the type code, denoting which address space
* bbbbbbbb is the 8-bit bus number
* ddddd is the 5-bit device number
* fff is the 3-bit function number
* rrrrrrrr is the 8-bit register number
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*
* The physical size format is:
*
* pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_size_low cell: llllllll llllllll llllllll llllllll
*
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*/
struct pci_phys_spec {
};
typedef struct pci_phys_spec pci_regspec_t;
/*
* PCI masks for pci_phy_hi of PCI 1275 address cell.
*/
#define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M)
#define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M)
/*
* PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
*/
#define PCI_ADDR_MASK PCI_REG_ADDR_M
/*
* PCI Expansion ROM Header Format
*/
/*
* PCI Data Structure
*
* The PCI Data Structure is located within the first 64KB
* of the ROM image and must be DWORD aligned.
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_H */