/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCI_H
#define _SYS_PCI_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Configuration Header offsets
*/
/*
* Header type 0 offsets
*/
/*
* PCI to PCI bridge configuration space header format
*/
/*
* PCI to PCI bridge control register (0x3e) format
*/
/*
* Header type 2 (Cardbus) offsets
*/
/*
* PCI command register bits
*/
/*
* PCI Interrupt pin value
*/
/*
* PCI status register bits
*/
/*
* DEVSEL timing values
*/
/*
* BIST values
*/
/*
* PCI class codes
*/
/*
* PCI Sub-class codes - base class 0x0 (no new devices should use this code).
*/
/*
* PCI Sub-class codes - base class 0x1 (mass storage controllers)
*/
/*
* programming interface for IDE (subclass 1)
*/
/*
* programming interface for ATA (subclass 5)
*/
/*
* programming interface for ATA (subclass 6) for SATA
*/
/*
* programming interface for ATA (subclass 7) for SAS
*/
/*
* PCI Sub-class codes - base class 0x2 (Network controllers)
*/
/*
* PCI Sub-class codes - base class 03 (display controllers)
*/
/*
* programming interface for display for display class (subclass 0) VGA ctrlrs
*/
/*
* PCI Sub-class codes - base class 0x4 (multi-media devices)
*/
/*
* PCI Sub-class codes - base class 0x5 (memory controllers)
*/
/*
* PCI Sub-class codes - base class 0x6 (Bridge devices)
*/
/*
* programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 09)
* Semi-transparent PCI-to-PCI bridge
*/
/* facing system processor */
/* facing system processor */
/*
* programming interface for Bridges class 0x6 (subclass 0B) AS bridge
*/
/*
* PCI Sub-class codes - base class 0x7 (communication devices)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x0 (Serial)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x3 (Modem)
*/
/*
* PCI Sub-class codes - base class 0x8
*/
/*
* Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x2 (timer)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
*/
/*
* PCI Sub-class codes - base class 0x9
*/
/*
* Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
*/
/*
* PCI Sub-class codes - base class 0xA
*/
/*
* PCI Sub-class codes - base class 0xB
*/
/*
* PCI Sub-class codes - base class 0xC (Serial Controllers)
*/
/*
* Programming interfaces for class 0xC / subclass 0x0 (Firewire)
*/
/*
* Programming interfaces for class 0xC / subclass 0x3 (USB controller)
*/
/*
* Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
*/
/*
* PCI Sub-class codes - base class 0xD (Wireless controllers)
*/
/*
* Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
*/
/*
* PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
*/
/*
* PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
*/
/*
* PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
*/
/*
* PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
*/
/* time and freq test ctrlr */
/* PCI header decode */
/*
* Base register bit definitions.
*/
/*
* Capabilities linked list entry offsets
*/
/*
* Capability identifier values
*/
/*
* Capability next entry pointer values
*/
/*
* PCI power management (PM) capability entry offsets
*/
/*
* PM capabilities values - 2 bytes
*/
/*
*/
/*
* PM PMCSR PCI to PCI bridge support extension values - 1 byte
*/
/*
* PCI-X capability related definitions
*/
/*
* PCI-X bridge capability related definitions
*/
/*
* PCIX capabilities values
*/
/*
* PCIX ECC Phase Values
*/
/*
* PCI-X Command Encoding
*/
#if defined(_BIT_FIELDS_LTOH)
typedef struct pcix_attr {
r :1;
} pcix_attr_t;
#elif defined(_BIT_FIELDS_HTOL)
typedef struct pcix_attr {
uint32_t r :1,
} pcix_attr_t;
#else
#error "bit field not defined"
#endif
/*
* PCI Hotplug capability entry offsets
*
* SHPC based PCI hotplug controller registers accessed via the DWORD
* select and DATA registers in PCI configuration space relative to the
* PCI HP capibility pointer.
*/
/* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
#define PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT 0
/* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
#define PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT 0
/* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
/* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
/* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
/* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
/* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
/* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
/* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability masks and shifts
*/
/*
* PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
*/
/*
* PCI Message Signalled Interrupts: other interesting constants
*/
/*
* PCI Slot Id Capabilities, 2 bytes
*/
/* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
/*
* HyperTransport Capabilities; each HT cap uses the same PCI cap id of
* PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT
* Interface types, only bits [15:13] are used.
*/
/*
* other interesting PCI constants
*/
/*
* pci bus range definition
*/
typedef struct pci_bus_range {
/*
* The following typedef is used to represent an entry in the "ranges"
* property of a pci hostbridge device node.
*/
typedef struct pci_ranges {
} pci_ranges_t;
/*
* The following typedef is used to represent an entry in the "ranges"
* property of a pci-pci bridge device node.
*/
typedef struct {
} ppb_ranges_t;
/*
* This structure represents one entry of the 1275 "reg" property and
* "assigned-addresses" property for a PCI node. For the "reg" property, it
* may be one of an arbitrary length array for devices with multiple address
* windows. For the "assigned-addresses" property, it denotes an assigned
* physical address on the PCI bus. It may be one entry of the six entries
* for devices with multiple base registers.
*
* The physical address format is:
*
* Bit#: 33222222 22221111 11111100 00000000
* 10987654 32109876 54321098 76543210
*
* pci_phys_hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
* pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_phys_low cell: llllllll llllllll llllllll llllllll
*
* n is 0 if the address is relocatable, 1 otherwise
* p is 1 if the addressable region is "prefetchable", 0 otherwise
* t is 1 if the address is aliased (for non-relocatable I/O), below
* 1MB (for mem), or below 64 KB (for relocatable I/O).
* ss is the type code, denoting which address space
* bbbbbbbb is the 8-bit bus number
* ddddd is the 5-bit device number
* fff is the 3-bit function number
* rrrrrrrr is the 8-bit register number
* should be zero for non-relocatable, when ss is 01, or 10
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*
* The physical size format is:
*
* pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_size_low cell: llllllll llllllll llllllll llllllll
*
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*/
struct pci_phys_spec {
};
/*
* PCI masks for pci_phy_hi of PCI 1275 address cell.
*/
/*
* PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
*/
/*
* PCI Expansion ROM Header Format
*/
/*
* PCI Data Structure
*
* The PCI Data Structure is located within the first 64KB
* of the ROM image and must be DWORD aligned.
*/
/*
* we recognize the non transparent bridge child nodes with the
* following property. This is specific to an implementation only.
* This property is specific to AP nodes only.
*/
/*
* If a bridge device provides its own config space access services,
* the following property must be defined for the node either by
* the driver or the OBP.
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_H */