pci.h revision 269473047d747f7815af570197e4ef7322d3632c
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCI_H
#define _SYS_PCI_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Configuration Header offsets
*/
/*
* Header type 0 offsets
*/
/*
* PCI to PCI bridge configuration space header format
*/
#define PCI_BCNF_LATENCY_TIMER 0x1b
#define PCI_BCNF_IO_BASE_LOW 0x1c
#define PCI_BCNF_IO_LIMIT_LOW 0x1d
#define PCI_BCNF_SEC_STATUS 0x1e
#define PCI_BCNF_MEM_BASE 0x20
#define PCI_BCNF_MEM_LIMIT 0x22
#define PCI_BCNF_PF_BASE_LOW 0x24
#define PCI_BCNF_PF_LIMIT_LOW 0x26
#define PCI_BCNF_PF_BASE_HIGH 0x28
#define PCI_BCNF_PF_LIMIT_HIGH 0x2c
#define PCI_BCNF_IO_BASE_HI 0x30
#define PCI_BCNF_IO_LIMIT_HI 0x32
#define PCI_BCNF_CAP_PTR 0x34
#define PCI_BCNF_ROM 0x38
#define PCI_BCNF_ILINE 0x3c
#define PCI_BCNF_IPIN 0x3d
#define PCI_BCNF_BCNTRL 0x3e
#define PCI_BCNF_BASE_NUM 0x2
/*
* PCI to PCI bridge control register (0x3e) format
*/
#define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1
#define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2
#define PCI_BCNF_BCNTRL_ISA_ENABLE 0x4
#define PCI_BCNF_BCNTRL_VGA_ENABLE 0x8
#define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20
#define PCI_BCNF_BCNTRL_DTO_STAT 0x400
#define PCI_BCNF_BCNTRL_RESET 0x0040
#define PCI_BCNF_BCNTRL_B2B_ENAB 0x0080
#define PCI_BCNF_IO_MASK 0xf0
#define PCI_BCNF_MEM_MASK 0xfff0
/*
* Header type 2 (Cardbus) offsets
*/
/*
* PCI command register bits
*/
#define PCI_COMM_SPEC_CYC 0x8
#define PCI_COMM_MEMWR_INVAL 0x10
#define PCI_COMM_PALETTE_SNOOP 0x20
#define PCI_COMM_PARITY_DETECT 0x40
#define PCI_COMM_WAIT_CYC_ENAB 0x80
#define PCI_COMM_SERR_ENABLE 0x100
#define PCI_COMM_BACK2BACK_ENAB 0x200
/*
* PCI Interrupt pin value
*/
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
/*
* PCI status register bits
*/
/*
* DEVSEL timing values
*/
#define PCI_STAT_DEVSELT_FAST 0x0000
#define PCI_STAT_DEVSELT_MEDIUM 0x0200
#define PCI_STAT_DEVSELT_SLOW 0x0400
/*
* BIST values
*/
#define PCI_BIST_SUPPORTED 0x80
#define PCI_BIST_GO 0x40
#define PCI_BIST_RESULT_M 0x0f
#define PCI_BIST_RESULT_OK 0x00
/*
* PCI class codes
*/
/*
* PCI Sub-class codes - base class 0x0 (no new devices should use this code).
*/
/*
* PCI Sub-class codes - base class 0x1 (mass storage controllers)
*/
/*
* programming interface for IDE (subclass 1)
*/
/*
* programming interface for ATA (subclass 5)
*/
/*
* programming interface for ATA (subclass 6) for SATA
*/
/*
* programming interface for ATA (subclass 7) for SAS
*/
/*
* PCI Sub-class codes - base class 0x2 (Network controllers)
*/
/*
* PCI Sub-class codes - base class 03 (display controllers)
*/
/*
* programming interface for display for display class (subclass 0) VGA ctrlrs
*/
/*
* PCI Sub-class codes - base class 0x4 (multi-media devices)
*/
/*
* PCI Sub-class codes - base class 0x5 (memory controllers)
*/
/*
* PCI Sub-class codes - base class 0x6 (Bridge devices)
*/
/*
* programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
*/
/*
* programming interface for Bridges class 0x6 (subclass 09)
* Semi-transparent PCI-to-PCI bridge
*/
/* facing system processor */
/* facing system processor */
/*
* programming interface for Bridges class 0x6 (subclass 0B) AS bridge
*/
/*
* PCI Sub-class codes - base class 0x7 (communication devices)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x0 (Serial)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
*/
/*
* Programming interfaces for class 0x7 / subclass 0x3 (Modem)
*/
/*
* PCI Sub-class codes - base class 0x8
*/
/*
* Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x2 (timer)
*/
/*
* Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
*/
/*
* PCI Sub-class codes - base class 0x9
*/
/*
* Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
*/
/*
* PCI Sub-class codes - base class 0xA
*/
/*
* PCI Sub-class codes - base class 0xB
*/
/*
* PCI Sub-class codes - base class 0xC (Serial Controllers)
*/
/*
* Programming interfaces for class 0xC / subclass 0x0 (Firewire)
*/
/*
* Programming interfaces for class 0xC / subclass 0x3 (USB controller)
*/
/*
* Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
*/
/*
* PCI Sub-class codes - base class 0xD (Wireless controllers)
*/
/*
* Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
*/
/*
* PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
*/
/*
* PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
*/
/*
* PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
*/
/*
* PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
*/
/* time and freq test ctrlr */
/* PCI header decode */
/*
* Base register bit definitions.
*/
/*
* Capabilities linked list entry offsets
*/
/*
* Capability identifier values
*/
/*
* Capability next entry pointer values
*/
/*
* PCI power management (PM) capability entry offsets
*/
/*
* PM capabilities values - 2 bytes
*/
/*
*/
/*
* PM PMCSR PCI to PCI bridge support extension values - 1 byte
*/
/*
* PCI-X capability related definitions
*/
/*
* PCI-X bridge capability related definitions
*/
#define PCI_PCIX_SEC_STATUS_ERR_MASK 0x3C
#define PCI_PCIX_BDG_STATUS_USC 0x80000
#define PCI_PCIX_BDG_STATUS_SCO 0x100000
#define PCI_PCIX_BDG_STATUS_SRD 0x200000
#define PCI_PCIX_BDG_STATUS_ERR_MASK 0x380000
/*
* PCIX capabilities values
*/
/*
* PCIX ECC Phase Values
*/
#define PCI_PCIX_ECC_PHASE_NOERR 0x0
#define PCI_PCIX_ECC_PHASE_FADDR 0x1
#define PCI_PCIX_ECC_PHASE_SADDR 0x2
#define PCI_PCIX_ECC_PHASE_ATTR 0x3
#define PCI_PCIX_ECC_PHASE_DATA32 0x4
#define PCI_PCIX_ECC_PHASE_DATA64 0x5
/*
* PCI-X Command Encoding
*/
#define PCI_PCIX_CMD_INTR 0x0
#define PCI_PCIX_CMD_SPEC 0x1
#define PCI_PCIX_CMD_IORD 0x2
#define PCI_PCIX_CMD_IOWR 0x3
#define PCI_PCIX_CMD_DEVID 0x5
#define PCI_PCIX_CMD_MEMRD_DW 0x6
#define PCI_PCIX_CMD_MEMWR 0x7
#define PCI_PCIX_CMD_MEMRD_BL 0x8
#define PCI_PCIX_CMD_MEMWR_BL 0x9
#define PCI_PCIX_CMD_CFRD 0xA
#define PCI_PCIX_CMD_CFWR 0xB
#define PCI_PCIX_CMD_SPL 0xC
#define PCI_PCIX_CMD_DADR 0xD
#define PCI_PCIX_CMD_MEMRDBL 0xE
#define PCI_PCIX_CMD_MEMWRBL 0xF
#if defined(_BIT_FIELDS_LTOH)
typedef struct pcix_attr {
rid :16,
tag :5,
ro :1,
ns :1,
r :1;
} pcix_attr_t;
#elif defined(_BIT_FIELDS_HTOL)
typedef struct pcix_attr {
uint32_t r :1,
ns :1,
ro :1,
tag :5,
rid :16,
lbc :8;
} pcix_attr_t;
#else
#error "bit field not defined"
#endif
/*
* PCI Hotplug capability entry offsets
*
* SHPC based PCI hotplug controller registers accessed via the DWORD
* select and DATA registers in PCI configuration space relative to the
* PCI HP capibility pointer.
*/
#define PCI_HP_DWORD_SELECT_OFF 0x2
#define PCI_HP_DWORD_DATA_OFF 0x4
#define PCI_HP_BASE_OFFSET_REG 0x00
#define PCI_HP_SLOTS_AVAIL_I_REG 0x01
#define PCI_HP_SLOTS_AVAIL_II_REG 0x02
#define PCI_HP_SLOT_CONFIGURATION_REG 0x03
#define PCI_HP_PROF_IF_SBCR_REG 0x04
#define PCI_HP_COMMAND_STATUS_REG 0x05
#define PCI_HP_IRQ_LOCATOR_REG 0x06
#define PCI_HP_SERR_LOCATOR_REG 0x07
#define PCI_HP_CTRL_SERR_INT_REG 0x08
#define PCI_HP_LOGICAL_SLOT_REGS 0x09
#define PCI_HP_VENDOR_SPECIFIC 0x28
/* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
#define PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT 0
#define PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT 8
#define PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT 16
#define PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT 24
#define PCI_HP_AVAIL_SPEED_MASK 0x1F
/* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
#define PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT 0
/* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
#define PCI_HP_SBCR_33MHZ_CONV_SPEED 0x0
#define PCI_HP_SBCR_66MHZ_CONV_SPEED 0x1
#define PCI_HP_SBCR_66MHZ_PCIX_SPEED 0x2
#define PCI_HP_SBCR_100MHZ_PCIX_SPEED 0x3
#define PCI_HP_SBCR_133MHZ_PCIX_SPEED 0x4
#define PCI_HP_SBCR_SPEED_MASK 0x7
/* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
#define PCI_HP_COMM_STS_ERR_INVALID_SPEED 0x80000
#define PCI_HP_COMM_STS_ERR_INVALID_COMMAND 0x40000
#define PCI_HP_COMM_STS_ERR_MRL_OPEN 0x20000
#define PCI_HP_COMM_STS_ERR_MASK 0xe0000
#define PCI_HP_COMM_STS_CTRL_BUSY 0x10000
#define PCI_HP_COMM_STS_SET_SPEED 0x40
/* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
#define PCI_HP_SERR_INT_GLOBAL_IRQ_MASK 0x1
#define PCI_HP_SERR_INT_GLOBAL_SERR_MASK 0x2
#define PCI_HP_SERR_INT_CMD_COMPLETE_MASK 0x4
#define PCI_HP_SERR_INT_ARBITER_SERR_MASK 0x8
#define PCI_HP_SERR_INT_CMD_COMPLETE_IRQ 0x10000
#define PCI_HP_SERR_INT_ARBITER_IRQ 0x20000
#define PCI_HP_SERR_INT_MASK_ALL 0xf
/* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
#define PCI_HP_SLOT_POWER_ONLY 0x1
#define PCI_HP_SLOT_ENABLED 0x2
#define PCI_HP_SLOT_DISABLED 0x3
#define PCI_HP_SLOT_STATE_MASK 0x3
#define PCI_HP_SLOT_MRL_STATE_MASK 0x100
#define PCI_HP_SLOT_66MHZ_CONV_CAPABLE 0x200
#define PCI_HP_SLOT_CARD_EMPTY_MASK 0xc00
#define PCI_HP_SLOT_66MHZ_PCIX_CAPABLE 0x1000
#define PCI_HP_SLOT_100MHZ_PCIX_CAPABLE 0x2000
#define PCI_HP_SLOT_133MHZ_PCIX_CAPABLE 0x3000
#define PCI_HP_SLOT_PCIX_CAPABLE_MASK 0x3000
#define PCI_HP_SLOT_PCIX_CAPABLE_SHIFT 12
#define PCI_HP_SLOT_PRESENCE_DETECTED 0x10000
#define PCI_HP_SLOT_ISO_PWR_DETECTED 0x20000
#define PCI_HP_SLOT_ATTN_DETECTED 0x40000
#define PCI_HP_SLOT_MRL_DETECTED 0x80000
#define PCI_HP_SLOT_POWER_DETECTED 0x100000
#define PCI_HP_SLOT_PRESENCE_MASK 0x1000000
#define PCI_HP_SLOT_ISO_PWR_MASK 0x2000000
#define PCI_HP_SLOT_ATTN_MASK 0x4000000
#define PCI_HP_SLOT_MRL_MASK 0x8000000
#define PCI_HP_SLOT_POWER_MASK 0x10000000
#define PCI_HP_SLOT_MRL_SERR_MASK 0x20000000
#define PCI_HP_SLOT_POWER_SERR_MASK 0x40000000
#define PCI_HP_SLOT_MASK_ALL 0x5f000000
/* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
#define PCI_HP_IRQ_CMD_COMPLETE 0x1
#define PCI_HP_IRQ_SLOT_N_PENDING 0x2
/* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
#define PCI_HP_IRQ_SERR_ARBITER_PENDING 0x1
#define PCI_HP_IRQ_SERR_SLOT_N_PENDING 0x2
/* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
#define PCI_HP_SLOT_CONFIG_MRL_SENSOR 0x40000000
#define PCI_HP_SLOT_CONFIG_ATTN_BUTTON 0x80000000
#define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT 16
#define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK 0x3FF
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
*/
/*
* PCI Message Signalled Interrupts (MSI) capability masks and shifts
*/
/*
* PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
*/
#define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */
/*
* PCI Message Signalled Interrupts: other interesting constants
*/
/*
* PCI Slot Id Capabilities, 2 bytes
*/
/* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
/*
* HyperTransport Capabilities; each HT cap uses the same PCI cap id of
* PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT
* Interface types, only bits [15:13] are used.
*/
#define PCI_HTCAP_TYPE_MASK 0xF800
#define PCI_HTCAP_TYPE_SHIFT 11
#define PCI_HTCAP_SLPRI_ID 0x00
#define PCI_HTCAP_HOSTSEC_ID 0x04
#define PCI_HTCAP_SWITCH_ID 0x08
#define PCI_HTCAP_INTCONF_ID 0x10
#define PCI_HTCAP_REVID_ID 0x11
#define PCI_HTCAP_UNITID_CLUMP_ID 0x12
#define PCI_HTCAP_ECFG_ID 0x13
#define PCI_HTCAP_ADDRMAP_ID 0x14
#define PCI_HTCAP_MSIMAP_ID 0x15
#define PCI_HTCAP_DIRROUTE_ID 0x16
#define PCI_HTCAP_VCSET_ID 0x17
#define PCI_HTCAP_RETRYMODE_ID 0x18
#define PCI_HTCAP_X86ENC_ID 0x19
#define PCI_HTCAP_GEN3_ID 0x1A
#define PCI_HTCAP_FUNCEXT_ID 0x1B
#define PCI_HTCAP_PM_ID 0x1C
#define PCI_HTCAP_SLPRI_TYPE /* 0x0000 */ \
#define PCI_HTCAP_HOSTSEC_TYPE /* 0x2000 */ \
#define PCI_HTCAP_SWITCH_TYPE /* 0x4000 */ \
#define PCI_HTCAP_INTCONF_TYPE /* 0x8000 */ \
#define PCI_HTCAP_REVID_TYPE /* 0x8800 */ \
#define PCI_HTCAP_UNITID_CLUMP_TYPE /* 0x9000 */ \
#define PCI_HTCAP_ECFG_TYPE /* 0x9800 */ \
#define PCI_HTCAP_ADDRMAP_TYPE /* 0xA000 */ \
#define PCI_HTCAP_MSIMAP_TYPE /* 0xA800 */ \
#define PCI_HTCAP_DIRROUTE_TYPE /* 0xB000 */ \
#define PCI_HTCAP_VCSET_TYPE /* 0xB800 */ \
#define PCI_HTCAP_RETRYMODE_TYPE /* 0xC000 */ \
#define PCI_HTCAP_X86ENC_TYPE /* 0xC800 */ \
#define PCI_HTCAP_GEN3_TYPE /* 0xD000 */ \
#define PCI_HTCAP_FUNCEXT_TYPE /* 0xD800 */ \
#define PCI_HTCAP_PM_TYPE /* 0xE000 */ \
#define PCI_HTCAP_MSIMAP_ENABLE 0x0001
#define PCI_HTCAP_MSIMAP_ENABLE_MASK 0x0001
#define PCI_HTCAP_ADDRMAP_MAPTYPE_MASK 0x600
#define PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT 9
#define PCI_HTCAP_ADDRMAP_NUMMAP_MASK 0xF
#define PCI_HTCAP_ADDRMAP_40BIT_ID 0x0
#define PCI_HTCAP_ADDRMAP_64BIT_ID 0x1
#define PCI_HTCAP_FUNCEXT_LEN_MASK 0xFF
/*
* other interesting PCI constants
*/
/*
* pci bus range definition
*/
typedef struct pci_bus_range {
/*
* The following typedef is used to represent an entry in the "ranges"
* property of a pci hostbridge device node.
*/
typedef struct pci_ranges {
} pci_ranges_t;
/*
* The following typedef is used to represent an entry in the "ranges"
* property of a pci-pci bridge device node.
*/
typedef struct {
} ppb_ranges_t;
/*
* This structure represents one entry of the 1275 "reg" property and
* "assigned-addresses" property for a PCI node. For the "reg" property, it
* may be one of an arbitrary length array for devices with multiple address
* windows. For the "assigned-addresses" property, it denotes an assigned
* physical address on the PCI bus. It may be one entry of the six entries
* for devices with multiple base registers.
*
* The physical address format is:
*
* Bit#: 33222222 22221111 11111100 00000000
* 10987654 32109876 54321098 76543210
*
* pci_phys_hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
* pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_phys_low cell: llllllll llllllll llllllll llllllll
*
* n is 0 if the address is relocatable, 1 otherwise
* p is 1 if the addressable region is "prefetchable", 0 otherwise
* t is 1 if the address is aliased (for non-relocatable I/O), below
* 1MB (for mem), or below 64 KB (for relocatable I/O).
* ss is the type code, denoting which address space
* bbbbbbbb is the 8-bit bus number
* ddddd is the 5-bit device number
* fff is the 3-bit function number
* rrrrrrrr is the 8-bit register number
* should be zero for non-relocatable, when ss is 01, or 10
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*
* The physical size format is:
*
* pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* pci_size_low cell: llllllll llllllll llllllll llllllll
*
* hh...hhh is the 32-bit unsigned number
* ll...lll is the 32-bit unsigned number
*/
struct pci_phys_spec {
};
typedef struct pci_phys_spec pci_regspec_t;
/*
* PCI masks for pci_phy_hi of PCI 1275 address cell.
*/
#define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M)
#define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M)
/*
* PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
*/
#define PCI_ADDR_MASK PCI_REG_ADDR_M
/*
* PCI Expansion ROM Header Format
*/
/*
* PCI Data Structure
*
* The PCI Data Structure is located within the first 64KB
* of the ROM image and must be DWORD aligned.
*/
/*
* we recognize the non transparent bridge child nodes with the
* following property. This is specific to an implementation only.
* This property is specific to AP nodes only.
*/
#define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect"
/*
* If a bridge device provides its own config space access services,
* the following property must be defined for the node either by
* the driver or the OBP.
*/
#define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect"
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_H */