/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_RXDMA_HW_H
#define _SYS_NXGE_NXGE_RXDMA_HW_H
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
#include <nxge_hw.h>
/*
* NIU: Receive DMA Channels
*/
/* Receive DMA Clock Divider */
typedef union _rx_dma_ck_div_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* Default Port Receive DMA Channel (RDC)
*/
/* For the default port RDC and RDC table */
typedef union _def_pt_rdc_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rdc_tbl_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* RDC: 32 bit Addressing mode
*/
typedef union _rx_addr_md_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* RDC: Port Scheduler
*/
#define PT_DRR_WT_SHIFT 0
typedef union _pt_drr_wt_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* Port FIFO Usage */
typedef union _pt_use_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* RDC: Partitioning Support
* (Each of the following registers is for each RDC)
* Please refer to nxge_hw.h for the common logical
* page configuration register definitions.
*/
/* RX and TX have the same definitions */
/* RDC: Weighted Random Early Discard */
/* Weighted Random */
typedef union _red_ran_init_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* Buffer block descriptor
*/
typedef struct _rx_desc_t {
/*
* RDC: RED Parameter
* (Each DMC has one RED register)
*/
/* the layout of this register is rx_disc_cnt_t */
/* RDC: RED parameters */
typedef union _rdc_red_para_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* RDC: Receive DMA Datapath Configuration
* The following register definitions are for
* each DMA channel. Each DMA CSR is 512 bytes
* (0x200).
*/
typedef union _rxdma_cfig1_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* NOTE: offset256 valid only for Neptune-L and RF-NIU */
typedef union _rxdma_cfig2_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* RDC: Receive Block Ring Configuration
* The following register definitions are for
* each DMA channel.
*/
typedef union _rbr_cfig_a_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
} bits;
typedef union _rbr_cfig_b_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rbr_kick_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rbr_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rbr_hdh_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rbr_hdl_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* Receive Completion Ring (RCR)
*/
typedef union _rcr_entry_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
} bits;
/*
* Receive Completion Ring Configuration.
* (for each DMA channel)
*/
#if OLD
#endif
/* (DMC + 0x00050) */
/* (DMC + 0x00058) */
/* (DMC + 0x00060) */
/* Receive DMA Interrupt Behavior: Event Mask (DMC + 0x00068) */
/* Receive DMA Control and Status (DMC + 0x00070) */
/* the following are write 1 to clear bits */
/* Receive DMA Interrupt Behavior: Force an update to RCR (DMC + 0x00078 */
/* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00080 */
/* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00088 */
typedef union _rcrcfig_a_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
} bits;
typedef union _rcrcfig_b_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rcrstat_a_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rcrstat_b_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rcrstat_c_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* Receive DMA Event Mask */
typedef union _rx_dma_ent_msk_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* Receive DMA Control and Status */
typedef union _rx_dma_ctl_stat_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} hdw;
#endif
} bits;
typedef union _rcr_flsh_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rx_dma_loga_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rx_dma_logb_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef struct _rxdma_mailbox_t {
typedef union _rx_disc_cnt_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#if OLD
/*
* RBR Empty: If the RBR is empty or the prefetch buffer is empty,
* packets will be discarded (Each RBR has one).
* (16 channels, 0x200)
*/
typedef union _rdc_pre_empty_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#endif
/* WRED discard count register (16, 0x40) */
typedef union _red_disc_cnt_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rdmc_par_err_log {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* Used for accessing RDMC Memory */
typedef union _rdmc_mem_addr {
struct {
#if defined(_BIG_ENDIAN)
#endif
#define RDMC_MEM_ADDR_PREFETCH 0
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rdmc_mem_data {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rdmc_mem_access {
typedef union _rx_ctl_dat_fifo {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union _rx_training_vect {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/*
* Receive Packet Header Format
* Packet header before the packet.
* The minimum is 2 bytes and the max size is 18 bytes.
*/
/*
* Packet header format 0 (2 bytes).
*/
typedef union _rx_pkt_hdr0_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
/*
* Packet header format 1.
*/
typedef union _rx_pkt_hdr1_b0_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b1_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b2_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b3_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b4_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b5_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b6_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b7_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b8_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b9_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b10_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b11_b12_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b13_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
typedef union _rx_pkt_hdr1_b14_b17_t {
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} bits;
/* Receive packet header 1 format (18 bytes) */
typedef struct _rx_pkt_hdr_t {
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_RXDMA_HW_H */