/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#ifndef _SYS_NXGE_NXGE_PHY_HW_H
#define _SYS_NXGE_NXGE_PHY_HW_H
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
/*
* for on-chip serdes. So here the starting port is 6.
*/
/*
* Description of BCM_PHY_ID_MASK:
* The first nibble (bits 0 through 3) is changed with every revision
* of the silicon. So these bits are masked out to support future revisions
* of the same chip. The third nibble (bits 8 through 11) is changed for
* different chips of the same family. So these bits are masked out to
* support chips of the same family.
*/
/*
* The default value is 0xa19410, after masking out model and revision
* (bits[9:0]) use 0xa19400 for any model or revision of the TN1010
*/
/*
* Description of TN1010_DEV_ID_MASK:
* The device ID assigned to Teranetics is stored in TN1010 register
* 1.2 and register 1.3 except bits[9:4] of register 1.3 for model number
* and bits[3:0] of register 1.3 for revision numbers. Use mask 0xfffffc00
* to mask off model number and revision number and keep TN1010's device
* identifier
*/
/*
* The Netlogic device ID and mask:
* The device ID assigned to Netlogic is stored in AEL2020 register
* 1.2 and register 1.3 except bits[7:4] of register 1.3 have the model number
* and bits[3:0] of register 1.3 have the revision number. Use mask 0xffffff00
* to mask off model number and revision number and keep AEL2020 device
* identifier
*/
/* IEEE802.3 Clause45 and Clause22 MDIO port addresses */
/*
* Phy address for the second NIU port on Goa NEM card can be either
* 20 or 17
*/
/*
* Phy addresses for AEL2020 used in QSFP for RF systems
*/
/*
* Phy addresses for Maramba support. Support for P0 will eventually
* be removed.
*/
/* Definitions for BCM 5464R PHY chip */
/* MARVELL PHY Definitions */
/* REG Offsets */
/* MRVL88X2011 register control */
/*
* MII Register 16: PHY Extended Control Register
*/
typedef union _mii_phy_ecr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 17: PHY Extended Status Register
*/
typedef union _mii_phy_esr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 18: Receive Error Counter Register
*/
typedef union _mii_rxerr_cnt_t {
struct {
} bits;
/*
* MII Register 19: False Carrier Sense Counter Register
*/
typedef union _mii_falsecs_cnt_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 20: Receiver NOT_OK Counter Register
*/
typedef union _mii_rx_notok_cnt_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 21: Expansion Register Data Register
*/
typedef union _mii_er_data_t {
struct {
} bits;
/*
* MII Register 23: Expansion Register Access Register
*/
typedef union _mii_er_acc_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 24: Auxiliary Control Register
*/
typedef union _mii_aux_ctl_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 25: Auxiliary Status Summary Register
*/
typedef union _mii_aux_s_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 26, 27: Interrupt Status and Mask Registers
*/
typedef union _mii_intr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 28: Register 1C Access Register
*/
typedef union _mii_misc_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
*/
typedef union _mii_misc1_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 30: Test Register 1
*/
typedef union _mii_test1_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/* Definitions of BCM8704 */
#define BCM8704_PMD_CONTROL_REG 0
#define BCM8704_PCS_CONTROL_REG 0
#define BCM8704_PHYXS_CONTROL_REG 0
/* Rx Channel Control1 Register bits */
typedef union _phyxs_control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
typedef union _control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
typedef union _pmd_tx_control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
typedef union _optics_dcntr {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */
/* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */
/* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */
/* Teranetics TN1010 Definitions */
/* Teranetics TN1010 PHY MMD Addresses */
/* TN1010 PCS Control Register */
typedef union _tn1010_pcs_ctrl {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/* TN1010 PHY XS Control Register */
typedef union _tn1010_phyxs_ctrl {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/* TN1010 VENDOR MMD1 GPHY Control register 30.310 */
#define TN1010_PMD_CONTROL_REG 0
#define TN1010_PCS_CONTROL_REG 0
#define TN1010_PHYXS_CONTROL_REG 0
#define TN1010_AUTONEG_CONTROL_REG 0
#define TN1010_VENDOR_MMD1_CONTROL_REG 0
/* Bits definitions of TN1010_AUTONEG_CONTROL_REG */
/* Bits definitions of TN1010_PHYXS_CONTROL_REG */
/*
* Shift right 6 bits so bits[7:6] becomes [1:0].
* Bits[7:6] of TN1010_VENDOR_MND1_STATUS_REG are for autoneg status
* 00 in progress
* 01 completed
* 10 reserved
* 11 failed
*/
/* Bit 4 of TN1010_VENDOR_MMD1_STATUS_REG is speed. 0: 10G, 1: 1G */
/* Shift right 4 bits so bit4 becomes bit0 */
/*
* Definitions for Netlogic AEL2020 PHY
*/
#define NLP2020_PMA_PMD_CTL_REG 0
#define NLP2020_UC_CTL_START 0
/*
* QSFP defines
*/
typedef enum {
/*
* struct for PHY addr-value pairs
*/
typedef struct _nxge_nlp_initseq_t {
/*
* struct for PHY dev, register and value triple properties
*/
typedef struct _nxge_phy_mdio_val_t {
/*
* struct for PHY register configurable property
*/
typedef struct _nxge_phy_prop_t {
int cnt;
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_PHY_HW_H */