nxge_mac_hw.h revision 2d17280b54ae99042345312e1d825acc6d977fd5
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_MAC_NXGE_MAC_HW_H
#define _SYS_MAC_NXGE_MAC_HW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
/* -------------------------- From May's template --------------------------- */
#define NXGE_1GETHERMIN 255
#define NXGE_ETHERMIN 97
#define NXGE_MAX_HEADER 250
/* Hardware reset */
typedef enum {
NXGE_TX_DISABLE, /* Disable Tx side */
NXGE_RX_DISABLE, /* Disable Rx side */
NXGE_CHIP_RESET /* Full chip reset */
} nxge_reset_t;
/* linkup */
#define FILTER_M_CTL 0xDCEF1
#define HASH_BITS 8
#define HASH_REG_WIDTH 16
#define BROADCAST_HASH_WORD 0x0f
#define BROADCAST_HASH_BIT 0x8000
/* Number of multicast filter regs */
/* -------------------------------------------------------------------------- */
#define XMAC_PORT_0 0
#define XMAC_PORT_1 1
#define BMAC_PORT_0 2
#define BMAC_PORT_1 3
#define MAC_ADDR_REG_MASK 0xFFFF
/*
* Neptune port PHY type and Speed encoding.
*
* Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits
* speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed
* and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the
* speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy
* type encoding for the ports 0 thru 3.
*
* p3phy p2phy p1phy p0phy p3spd p2spd p1spd p0spd
* | | | | | | | |
* --- --- --- --- --- --- --- ---
* / \ / \ / \ / \ / \ / \ / \ / \
* 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
*/
#define NXGE_PORT_SPD_NONE 0x0
#define NXGE_PORT_SPD_1G 0x1
#define NXGE_PORT_SPD_10G 0x2
#define NXGE_PORT_SPD_RSVD 0x7
#define NXGE_PHY_NONE 0x0
#define NXGE_PHY_COPPER 0x1
#define NXGE_PHY_FIBRE 0x2
#define NXGE_PHY_SERDES 0x3
#define NXGE_PHY_RGMII_FIBER 0x4
#define NXGE_PHY_RSVD 0x7
#define NXGE_PORT_SPD_SHIFT 0
#define NXGE_PORT_SPD_MASK 0x0f
#define NXGE_PHY_SHIFT 16
#define NXGE_PHY_MASK 0x0f0000
#define NXGE_PORT_1G_COPPER (NXGE_PORT_SPD_1G | \
#define NXGE_PORT_10G_COPPER (NXGE_PORT_SPD_10G | \
#define NXGE_PORT_1G_FIBRE (NXGE_PORT_SPD_1G | \
(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
#define NXGE_PORT_10G_FIBRE (NXGE_PORT_SPD_10G | \
(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
#define NXGE_PORT_1G_SERDES (NXGE_PORT_SPD_1G | \
#define NXGE_PORT_10G_SERDES (NXGE_PORT_SPD_10G | \
#define NXGE_PORT_1G_RGMII_FIBER (NXGE_PORT_SPD_1G | \
#define NXGE_PORT_NONE (NXGE_PORT_SPD_NONE | \
(NXGE_PHY_NONE << NXGE_PHY_SHIFT))
#define NXGE_PORT_RSVD (NXGE_PORT_SPD_RSVD | \
(NXGE_PHY_RSVD << NXGE_PHY_SHIFT))
#define NXGE_PORT_TYPE_SHIFT 4
/* Network Modes */
typedef enum nxge_network_mode {
NET_2_10GE_FIBER = 1,
typedef enum nxge_port {
PORT_TYPE_XMAC = 1,
} nxge_port_t;
typedef enum nxge_port_mode {
PORT_1G_COPPER = 1,
typedef enum nxge_linkchk_mode {
LINKCHK_INTR = 1,
typedef enum {
typedef enum {
typedef enum {
} xcvr_inuse_t;
/* macros for port offset calculations */
#define PORT_1_OFFSET 0x6000
#define PORT_GT_1_OFFSET 0x4000
/* XMAC address macros */
#define XMAC_ADDR_OFFSET_0 0
#define XMAC_ADDR_OFFSET_1 0x6000
#define XMAC_ADDR_OFFSET(port_num)\
#define XMAC_PORT_ADDR(port_num)\
/* BMAC address macros */
#define BMAC_ADDR_OFFSET_2 0x0C000
#define BMAC_ADDR_OFFSET_3 0x10000
#define BMAC_ADDR_OFFSET(port_num)\
#define BMAC_PORT_ADDR(port_num)\
/* PCS address macros */
#define PCS_ADDR_OFFSET_0 0x04000
#define PCS_ADDR_OFFSET_1 0x0A000
#define PCS_ADDR_OFFSET_2 0x0E000
#define PCS_ADDR_OFFSET_3 0x12000
#define PCS_ADDR_OFFSET(port_num)\
((port_num <= 1) ? \
#define PCS_PORT_ADDR(port_num)\
/* XPCS address macros */
#define XPCS_ADDR_OFFSET_0 0x02000
#define XPCS_ADDR_OFFSET_1 0x08000
#define XPCS_ADDR_OFFSET(port_num)\
#define XPCS_PORT_ADDR(port_num)\
/* ESR address macro */
#define ESR_ADDR_OFFSET 0x14000
/* MIF address macros */
#define MIF_ADDR_OFFSET 0x16000
/* BMAC registers offset */
/* cfg register bitmap */
typedef union _btxmac_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _brxmac_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
typedef union _bxif_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* (own da, add filter, fc) */
/* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */
/* XMAC registers offset */
/* xmac config bit fields */
typedef union _xmac_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xmac_cfg_t, *p_xmac_cfg_t;
/* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */
/* MIF registers offset */
#define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */
/* PCS registers offset */
#define PCS_MII_CTRL_REG 0 /* PCS MII control reg */
#define XPCS_CTRL_1_REG 0 /* Control */
#define XPCS_STATUS_1_REG 0x008
#define XPCS_SPEED_ABILITY_REG 0x018
#define XPCS_DEV_IN_PKG_REG 0x020
#define XPCS_CTRL_2_REG 0x028
#define XPCS_STATUS_2_REG 0x030
#define XPCS_STATUS_REG 0x040
#define XPCS_TEST_CTRL_REG 0x048
#define XPCS_CFG_VENDOR_1_REG 0x050
#define XPCS_DIAG_VENDOR_2_REG 0x058
#define XPCS_MASK_1_REG 0x060
#define XPCS_PKT_CNTR_REG 0x068
#define XPCS_TX_STATE_MC_REG 0x070
#define XPCS_DESKEW_ERR_CNTR_REG 0x078
#define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080
#define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088
#define XPCS_TRAINING_VECTOR_REG 0x090
/* ESR registers offset */
#define ESR_RESET_REG 0
#define ESR_CONFIG_REG 0x008
#define ESR_0_PLL_CONFIG_REG 0x010
#define ESR_0_CONTROL_REG 0x018
#define ESR_0_TEST_CONFIG_REG 0x020
#define ESR_1_PLL_CONFIG_REG 0x028
#define ESR_1_CONTROL_REG 0x030
#define ESR_1_TEST_CONFIG_REG 0x038
#define ESR_ENET_RGMII_CFG_REG 0x040
#define ESR_INTERNAL_SIGNALS_REG 0x800
#define ESR_DEBUG_SEL_REG 0x808
/* Reset Register */
/* Tx MAC Status Register */
/* Rx MAC Status Register */
/* MAC Control Status Register */
#define MAC_CTRL_PAUSE_TIME_SHIFT 16
/* Tx MAC Configuration Register */
/* Rx MAC Configuration Register */
#define MAC_RX_MAC_REG_RW_TEST_SHIFT 10
/* MAC Control Configuration Register */
/* MAC XIF Configuration Register */
/* MAC IPG Registers */
/* MAC Max Frame Size Register */
#define BMAC_MAX_BURST_SHIFT 16
#define BMAC_MAX_FRAME_SHIFT 0
/* MAC Preamble size register */
#define BMAC_PA_SIZE_MASK 0x000003FF
/* # of preable bytes TxMAC sends at the beginning of each frame */
/*
* mac address registers:
* register contains comparison
* -------- -------- ----------
* 0 16 MSB of primary MAC addr [47:32] of DA field
* 1 16 middle bits "" [31:16] of DA field
* 2 16 LSB "" [15:0] of DA field
* 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field
* 4*x 16 middle bits "" [31:16]
* 5*x 16 LSB "" [15:0]
* 42 16 MSB of MAC CTRL addr [47:32] of DA.
* 43 16 middle bits "" [31:16]
* 44 16 LSB "" [15:0]
* MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
* if there is a match, MAC will set the bit for alternative address
* filter pass [15]
*
* here is the map of registers given MAC address notation: a:b:c:d:e:f
* ab cd ef
* primary addr reg 2 reg 1 reg 0
* alt addr 1 reg 5 reg 4 reg 3
* alt addr x reg 5*x reg 4*x reg 3*x
* | | | |
* | | | |
* alt addr 7 reg 23 reg 22 reg 21
* ctrl addr reg 44 reg 43 reg 42
*/
#define BMAC_ALT_ADDR_BASE 0x118
/* hash table registers */
#define MAC_MAX_HASH_ENTRY 16
/* 27-bit register has the current state for key state machines in the MAC */
#define MAC_SM_RLM_MASK 0x07800000
#define MAC_SM_RLM_SHIFT 23
#define MAC_SM_RX_FC_MASK 0x00700000
#define MAC_SM_RX_FC_SHIFT 20
#define MAC_SM_TLM_MASK 0x000F0000
#define MAC_SM_TLM_SHIFT 16
#define MAC_SM_ENCAP_SM_MASK 0x0000F000
#define MAC_SM_ENCAP_SM_SHIFT 12
#define MAC_SM_TX_REQ_MASK 0x00000C00
#define MAC_SM_TX_REQ_SHIFT 10
#define MAC_SM_TX_FC_MASK 0x000003C0
#define MAC_SM_TX_FC_SHIFT 6
#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
#define BMAC_ADDR0_CMPEN 0x00000001
#define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x))
/* MAC Host Info Table Registers */
/*
* ********************* XMAC registers *********************************
*/
/* Reset Register */
/* XTX MAC Status Register */
/* XRX MAC Status Register */
#define XMAC_CTRL_PAUSE_TIME_SHIFT 16
/* XMAC Configuration Register */
/* XTX MAC config bits */
/* XRX MAC config bits */
/* MAC transceiver (XIF) configuration registers */
#define XMAC_XIF_MII_MODE_SHIFT 27
#define XMAC_XIF_XGMII_MODE 0x00
#define XMAC_XIF_GMII_MODE 0x01
#define XMAC_XIF_MII_MODE 0x02
#define XMAC_XIF_ILLEGAL_MODE 0x03
/* IPG register */
#define XMAC_IPG_VALUE_SHIFT 0
#define XMAC_IPG_VALUE1_SHIFT 8
#define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000
#define XMAC_IPG_STRETCH_RATIO_SHIFT 16
#define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000
#define XMAC_IPG_STRETCH_CONST_SHIFT 21
#define IPG_12_15_BYTE 3
#define IPG_16_19_BYTE 4
#define IPG_20_23_BYTE 5
#define IPG1_12_BYTES 10
#define IPG1_13_BYTES 11
#define IPG1_14_BYTES 12
#define IPG1_15_BYTES 13
#define IPG1_16_BYTES 14
#define XMAC_MIN_TX_FRM_SZ_SHIFT 0
#define XMAC_SLOT_TIME_SHIFT 10
#define XMAC_MIN_RX_FRM_SZ_SHIFT 20
/* State Machine Register */
#define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007
#define XMAC_SM_TX_LNK_MGMT_SHIFT 0
#define XMAC_SM_SOP_DETECT 0x00000008
#define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030
#define XMAC_SM_LNK_FLT_SIG_SHIFT 4
#define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040
#define XMAC_SM_XGMII_MD_RX_LNK 0x00000080
#define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100
#define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200
#define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00
#define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10
#define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000
#define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18
#define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000
#define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23
#define XMAC_SM_TXFIFO_FULL_CLK 0x10000000
#define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000
#define XMAC_SM_RXFIFO_FULL_CLK 0x40000000
#define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000
/* Internal Signals 1 Register */
#define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F
#define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0
#define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010
#define XMAC_IS1_OPP_TXMAC_TAG 0x00000020
#define XMAC_IS1_OPP_TXMAC_ACK 0x00000040
#define XMAC_IS1_TXMAC_OPP_REQ 0x00000080
#define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00
#define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8
#define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000
#define XMAC_IS1_RXMAC_IPP_TAG 0x20000000
#define XMAC_IS1_IPP_RXMAC_REQ 0x40000000
#define XMAC_IS1_RXMAC_IPP_ACK 0x80000000
/* Internal Signals 2 Register */
#define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F
#define XMAC_IS2_TX_HB_TIMER_SHIFT 0
#define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0
#define XMAC_IS2_RX_HB_TIMER_SHIFT 4
#define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00
#define XMAC_IS2_XPCS_RXC_SHIFT 8
#define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000
#define XMAC_IS2_XPCS_TXC_SHIFT 16
#define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000
#define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000
/* Register size masking */
#define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF
#define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF
#define XRXMAC_CRC_ER_CNT_MASK 0x000000FF
#define XRXMAC_MPSZER_CNT_MASK 0x000000FF
#define XRXMAC_CD_VIO_CNT_MASK 0x000000FF
#define XRXMAC_BT_CNT_MASK 0xFFFFFFFF
#define XRXMAC_HIST_CNT1_MASK 0x001FFFFF
#define XRXMAC_HIST_CNT2_MASK 0x001FFFFF
#define XRXMAC_HIST_CNT3_MASK 0x000FFFFF
#define XRXMAC_HIST_CNT4_MASK 0x0007FFFF
#define XRXMAC_HIST_CNT5_MASK 0x0003FFFF
#define XRXMAC_HIST_CNT6_MASK 0x0001FFFF
#define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF
#define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF
#define XRXMAC_FRAG_CNT_MASK 0x001FFFFF
#define XRXMAC_AL_ER_CNT_MASK 0x000000FF
#define XMAC_LINK_FLT_CNT_MASK 0x000000FF
#define BTXMAC_FRM_CNT_MASK 0x001FFFFF
#define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF
#define RXMAC_FRM_CNT_MASK 0x0000FFFF
#define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF
#define BMAC_AL_ER_CNT_MASK 0x0000FFFF
#define MAC_LEN_ER_CNT_MASK 0x0000FFFF
#define BMAC_CRC_ER_CNT_MASK 0x0000FFFF
#define BMAC_CD_VIO_CNT_MASK 0x0000FFFF
#define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF
#define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF
#define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000
#define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16
#define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF
#define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000
#define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16
/* Alternate MAC address registers */
/* Max / Min parameters for Neptune MAC */
/* HostInfo entry for the unique MAC address */
#define XMAC_UNIQUE_HOST_INFO_ENTRY 17
#define BMAC_UNIQUE_HOST_INFO_ENTRY 0
/* HostInfo entry for the multicat address */
#define XMAC_MULTI_HOST_INFO_ENTRY 16
#define BMAC_MULTI_HOST_INFO_ENTRY 8
/* XMAC Host Info Register */
typedef union hostinfo {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} hostinfo_t;
typedef union hostinfo *hostinfo_pt;
#define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007
#define XMAC_HI_MAC_PREF 0x00000100
/*
* ******************** MIF registers *********************************
*/
/*
* 32-bit register serves as an instruction register when the MIF is
* programmed in frame mode. load this register w/ a valid instruction
* (as per IEEE 802.3u MII spec). poll this register to check for instruction
* execution completion. during a read operation, this register will also
* contain the 16-bit data returned by the transceiver. unless specified
* otherwise, fields are considered "don't care" when polling for
* completion.
*/
#define MIF_FRAME_PHY_ADDR_SHIFT 23
/* dev addr in Cl 45 */
#define MIF_FRAME_REG_ADDR_SHIFT 18
/* Clause 45 frame field values */
#define FRAME45_ST 0
#define FRAME45_OP_ADDR 0
#define FRAME45_OP_WRITE 1
#define FRAME45_OP_READ_INC 2
#define FRAME45_OP_READ 3
typedef union _mif_frame_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_frame_t;
#define MIF_CFG_POLL_REG_SHIFT 5
#define MIF_CFG_POLL_PHY_SHIFT 10
#define MIF_CFG_INDIRECT_MODE 0x0000800
/* used to decide if Cl 22 */
/* or Cl 45 frame is */
/* constructed. */
/* 1 = Clause 45,ST = '00' */
/* 0 = Clause 22,ST = '01' */
typedef union _mif_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_cfg_t;
#define MIF_POLL_STATUS_DATA_MASK 0xffff0000
#define MIF_POLL_STATUS_STAT_MASK 0x0000ffff
typedef union _mif_poll_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
#define MIF_POLL_MASK_MASK 0x0000ffff
typedef union _mif_poll_mask_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
#define MIF_STATUS_INIT_DONE_MASK 0x00000001
#define MIF_STATUS_XGE_ERR0_MASK 0x00000002
#define MIF_STATUS_XGE_ERR1_MASK 0x00000004
#define MIF_STATUS_PEU_ERR_MASK 0x00000008
#define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010
#define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020
typedef union _mif_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} mif_stat_t;
/* MIF State Machine Register */
#define MIF_SM_EXECUTION_SHIFT 0
#define MIF_SM_CONTROL_MASK_SHIFT 6
#define MIF_SM_MDI 0x00000200
#define MIF_SM_MDO 0x00000400
#define MIF_SM_MDO_EN 0x00000800
#define MIF_SM_MDC 0x00001000
#define MIF_SM_MDI_0 0x00002000
#define MIF_SM_MDI_1 0x00004000
#define MIF_SM_MDI_2 0x00008000
#define MIF_SM_PORT_ADDR_MASK 0x001f0000
#define MIF_SM_PORT_ADDR_SHIFT 16
#define MIF_SM_INT_SIG_MASK 0xffe00000
#define MIF_SM_INT_SIG_SHIFT 21
/*
* ******************** PCS registers *********************************
*/
/* PCS Registers */
typedef union _pcs_ctrl_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_ctrl_t;
typedef union _pcs_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_stat_t;
#define PCS_MII_ADVERT_RF_SHIFT 12
#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
typedef union _pcs_anar_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_anar_t, *p_pcs_anar_t;
#define PCS_CFG_SD_OVERRIDE 0x0002
#define PCS_CFG_JITTER_STUDY_SHIFT 4
typedef union _pcs_cfg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} pcs_cfg_t, *p_pcs_cfg_t;
/* used for diagnostic purposes. bits 20-22 autoclear on read */
#define PCS_SM_TX_STATE_SHIFT 0
#define PCS_SM_RX_STATE_SHIFT 4
#define PCS_SM_WORD_SYNC_STATE_SHIFT 8
#define PCS_SM_SEQ_DETECT_STATE_SHIFT 11
#define PCS_SM_LINK_STATE_SHIFT 13
typedef union _pcs_stat_mc_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/*
* control which network interface is used. no more than one bit should
* be set.
*/
#define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */
#define PCS_PACKET_COUNT_RX_SHIFT 16
/*
* ******************** XPCS registers *********************************
*/
/* XPCS Base 10G Control1 Register */
#define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2
typedef union _xpcs_ctrl1_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_ctrl1_t;
/* XPCS Base 10G Status1 Register (Read Only) */
#define XPCS_STATUS1_FAULT 0x0080
typedef union _xpcs_stat1_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat1_t;
/* XPCS Base Speed Ability Register. Indicates 10G capability */
#define XPCS_SPEED_ABILITY_10_GIG 0x0001
typedef union _xpcs_speed_ab_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base 10G Devices in Package Register */
#define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000
#define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000
#define XPCS_DEV_IN_PKG_DTE_XS 0x00000020
#define XPCS_DEV_IN_PKG_PHY_XS 0x00000010
#define XPCS_DEV_IN_PKG_PCS 0x00000008
#define XPCS_DEV_IN_PKG_WIS 0x00000004
#define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002
#define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000
typedef union _xpcs_dev_in_pkg_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base 10G Control2 Register */
#define XPCS_PSC_SEL_MASK 0x0003
#define PSC_SEL_10G_BASE_X_PCS 0x0001
typedef union _xpcs_ctrl2_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_ctrl2_t;
/* XPCS Base10G Status2 Register */
typedef union _xpcs_stat2_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat2_t;
/* XPCS Base10G Status Register */
typedef union _xpcs_stat_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_stat_t;
/* XPCS Base10G Test Control Register */
#define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004
#define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003
#define TEST_PATTERN_HIGH_FREQ 0
#define TEST_PATTERN_LOW_FREQ 1
#define TEST_PATTERN_MIXED_FREQ 2
typedef union _xpcs_test_ctl_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base10G Diagnostic Register */
#define XPCS_DIAG_EB_ALIGN_ERR3 0x40
#define XPCS_DIAG_EB_ALIGN_ERR2 0x20
#define XPCS_DIAG_EB_ALIGN_ERR1 0x10
#define XPCS_DIAG_EB_DESKEW_OK 0x08
#define XPCS_DIAG_EB_ALIGN_DET3 0x04
#define XPCS_DIAG_EB_ALIGN_DET2 0x02
#define XPCS_DIAG_EB_ALIGN_DET1 0x01
#define XPCS_DIAG_EB_DESKEW_LOSS 0
#define XPCS_DIAG_SYNC_3_INVALID 0x8
#define XPCS_DIAG_SYNC_2_INVALID 0x4
#define XPCS_DIAG_SYNC_1_INVALID 0x2
#define XPCS_DIAG_SYNC_IN_SYNC 0x1
#define XPCS_DIAG_SYNC_LOSS_SYNC 0
#define XPCS_RX_SM_RECEIVE_STATE 1
#define XPCS_RX_SM_FAULT_STATE 0
typedef union _xpcs_diag_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
} xpcs_diag_t;
/* XPCS Base10G Tx State Machine Register */
#define XPCS_TX_SM_SEND_UNDERRUN 0x9
#define XPCS_TX_SM_SEND_RANDOM_Q 0x8
#define XPCS_TX_SM_SEND_RANDOM_K 0x7
#define XPCS_TX_SM_SEND_RANDOM_A 0x6
#define XPCS_TX_SM_SEND_RANDOM_R 0x5
#define XPCS_TX_SM_SEND_Q 0x4
#define XPCS_TX_SM_SEND_K 0x3
#define XPCS_TX_SM_SEND_A 0x2
#define XPCS_TX_SM_SEND_SDP 0x1
#define XPCS_TX_SM_SEND_DATA 0
/* XPCS Base10G Configuration Register */
#define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78
#define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3
#define XPCS_CFG_BYPASS_SIG_DETECT 0x0004
#define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002
#define XPCS_CFG_XPCS_ENABLE 0x0001
typedef union _xpcs_config_t {
struct {
#if defined(_BIG_ENDIAN)
#elif defined(_LITTLE_ENDIAN)
#endif
} val;
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} w0;
#if defined(_LITTLE_ENDIAN)
#endif
} bits;
/* XPCS Base10G Mask1 Register */
/* XPCS Base10G Packet Counter */
#define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000
#define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16
#define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff
#define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0
/* XPCS Base10G TX State Machine status register */
#define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f
#define XPCS_DESKEW_ERR_CNTR_MASK 0xff
/* XPCS Base10G Lane symbol error counters */
#define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000
#define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff
#define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000
#define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff
#define XPCS_SYM_ERR_CNT_MULTIPLIER 16
/* ESR Reset Register */
#define ESR_RESET_1 2
#define ESR_RESET_0 1
/* ESR Configuration Register */
#define ESR_BLUNT_END_LOOPBACK 2
#define ESR_FORCE_SERDES_SERDES_RDY 1
/* ESR Neptune Serdes PLL Configuration */
#define ESR_PLL_CFG_FBDIV_0 0x1
#define ESR_PLL_CFG_FBDIV_1 0x2
#define ESR_PLL_CFG_FBDIV_2 0x4
#define ESR_PLL_CFG_HALF_RATE_0 0x8
#define ESR_PLL_CFG_HALF_RATE_1 0x10
#define ESR_PLL_CFG_HALF_RATE_2 0x20
#define ESR_PLL_CFG_HALF_RATE_3 0x40
#define ESR_PLL_CFG_1G_SERDES (ESR_PLL_CFG_FBDIV_0 | \
/* ESR Neptune Serdes Control Register */
#define ESR_CTL_EN_SYNCDET_0 0x00000001
#define ESR_CTL_EN_SYNCDET_1 0x00000002
#define ESR_CTL_EN_SYNCDET_2 0x00000004
#define ESR_CTL_EN_SYNCDET_3 0x00000008
#define ESR_CTL_OUT_EMPH_0_MASK 0x00000070
#define ESR_CTL_OUT_EMPH_0_SHIFT 4
#define ESR_CTL_OUT_EMPH_1_MASK 0x00000380
#define ESR_CTL_OUT_EMPH_1_SHIFT 7
#define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00
#define ESR_CTL_OUT_EMPH_2_SHIFT 10
#define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000
#define ESR_CTL_OUT_EMPH_3_SHIFT 13
#define ESR_CTL_LOSADJ_0_MASK 0x00070000
#define ESR_CTL_LOSADJ_0_SHIFT 16
#define ESR_CTL_LOSADJ_1_MASK 0x00380000
#define ESR_CTL_LOSADJ_1_SHIFT 19
#define ESR_CTL_LOSADJ_2_MASK 0x01c00000
#define ESR_CTL_LOSADJ_2_SHIFT 22
#define ESR_CTL_LOSADJ_3_MASK 0x0e000000
#define ESR_CTL_LOSADJ_3_SHIFT 25
#define ESR_CTL_RXITERM_0 0x10000000
#define ESR_CTL_RXITERM_1 0x20000000
#define ESR_CTL_RXITERM_2 0x40000000
#define ESR_CTL_RXITERM_3 0x80000000
#define ESR_CTL_1G_SERDES (ESR_CTL_EN_SYNCDET_0 | \
(0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \
(0x1 << ESR_CTL_LOSADJ_3_SHIFT))
/* ESR Neptune Serdes Test Configuration Register */
#define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003
#define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0
#define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c
#define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2
#define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030
#define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4
#define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0
#define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6
#define ESR_TSTCFG_LBTEST_PAD (ESR_PAD_LOOPBACK_CH3 | \
/* ESR Neptune Ethernet RGMII Configuration Register */
#define ESR_RGMII_PT0_IN_USE 0x00000001
#define ESR_RGMII_PT1_IN_USE 0x00000002
#define ESR_RGMII_PT2_IN_USE 0x00000004
#define ESR_RGMII_PT3_IN_USE 0x00000008
#define ESR_RGMII_REG_RW_TEST 0x00000010
/* ESR Internal Signals Observation Register */
#define ESR_SIG_MASK 0xFFFFFFFF
#define ESR_SIG_P0_BITS_MASK 0x33E0000F
#define ESR_SIG_P1_BITS_MASK 0x0C1F00F0
#define ESR_SIG_SERDES_RDY0_P0 0x20000000
#define ESR_SIG_DETECT0_P0 0x10000000
#define ESR_SIG_SERDES_RDY0_P1 0x08000000
#define ESR_SIG_DETECT0_P1 0x04000000
#define ESR_SIG_XSERDES_RDY_P0 0x02000000
#define ESR_SIG_XDETECT_P0_CH3 0x01000000
#define ESR_SIG_XDETECT_P0_CH2 0x00800000
#define ESR_SIG_XDETECT_P0_CH1 0x00400000
#define ESR_SIG_XDETECT_P0_CH0 0x00200000
#define ESR_SIG_XSERDES_RDY_P1 0x00100000
#define ESR_SIG_XDETECT_P1_CH3 0x00080000
#define ESR_SIG_XDETECT_P1_CH2 0x00040000
#define ESR_SIG_XDETECT_P1_CH1 0x00020000
#define ESR_SIG_XDETECT_P1_CH0 0x00010000
#define ESR_SIG_LOS_P1_CH3 0x00000080
#define ESR_SIG_LOS_P1_CH2 0x00000040
#define ESR_SIG_LOS_P1_CH1 0x00000020
#define ESR_SIG_LOS_P1_CH0 0x00000010
#define ESR_SIG_LOS_P0_CH3 0x00000008
#define ESR_SIG_LOS_P0_CH2 0x00000004
#define ESR_SIG_LOS_P0_CH1 0x00000002
#define ESR_SIG_LOS_P0_CH0 0x00000001
#define ESR_SIG_P0_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P0 | \
#define ESR_SIG_P1_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P1 | \
/* ESR Debug Selection Register */
#define ESR_DEBUG_SEL_MASK 0x00000003f
/* ESR Test Configuration Register */
#define ESR_NO_LOOPBACK_CH0 0x0
#define ESR_EWRAP_CH0 0x1
#define ESR_PAD_LOOPBACK_CH0 0x2
#define ESR_REVLOOPBACK_CH0 0x3
/* convert values */
#define NXGE_BASE(x, y) \
{ \
}
#ifdef __cplusplus
}
#endif
#endif /* _SYS_MAC_NXGE_MAC_HW_H */