/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_COMMON_H
#define _SYS_NXGE_NXGE_COMMON_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Default DMA configurations.
*/
/*
* Receive and Transmit DMA definitions
*/
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
/*
* Hypervisor to set up the logical pages
* and the driver must use contiguous memory.
*/
#endif
#ifdef _DMA_USES_VIRTADDR
#ifdef NIU_PA_WORKAROUND
#else
#endif
#else
#endif
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
#define NXGE_RBR_SPARE 0
#else
#if defined(__i386)
#else
#endif
#define NXGE_RBR_SPARE 0
#endif
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
#else
#ifndef NIU_PA_WORKAROUND
#if defined(_BIG_ENDIAN)
#else
#ifdef USE_RX_BIG_BUF
#else
#endif
#endif
#if defined(__i386)
#else
#endif
#else
#if defined(__i386)
#else
#endif
#endif
#endif
/* per receive DMA channel configuration data structure */
typedef struct nxge_rdc_cfg {
/* Partitioning, DMC function zero. */
/* WRED parameters, DMC function zero */
/* RXDMA configuration, DMC */
/* Software Reserved Packet Buffer Offset, DMC */
/* RBR Configuration A */
/* RBR Configuration B */
#define RBR_BKSIZE_4K 0
#define RBR_BUFSZ2_2K 0
#define RBR_BUFSZ1_1K 0
#define RBR_BUFSZ0_256B 0
/* Receive buffers added by the software */
/* Receive Completion Ring Configuration A */
/* Receive Completion Ring Configuration B */
/* Logical Device Group Number */
/* Receive DMA Channel Event Mask */
/* 32 bit (set to 1) or 64 bit (set to 0) addressing mode */
/*
* Per Transmit DMA Channel Configuration Data Structure (32 TDC)
*/
typedef struct nxge_tdc_cfg {
/* partitioning, DMC function zero (All 0s for non-partitioning) */
/* Transmit Ring Configuration */
/* TXDMA configuration, DMC */
/* Logical Device Group Number */
/* TXDMA event flags */
/* Transmit threshold before reclamation */
/* For reclaim: a wrap-around counter (packets transmitted) */
/* last packet with the mark bit set */
#define RDC_TABLE_ENTRY_METHOD_SEQ 0
/* per transmit DMA channel table group data structure */
typedef struct nxge_tdc_grp {
/* per receive DMA channel table group data structure */
typedef struct nxge_rdc_grp {
/* Common RDC and TDC configuration of DMC */
typedef struct _nxge_dma_common_cfg_t {
/* Transmit Ring */
/*
* VLAN and MAC table configurations:
* Each VLAN ID should belong to at most one RDC group.
* Each port could own multiple RDC groups.
* Each MAC should belong to one RDC group.
*/
typedef struct nxge_mv_cfg {
typedef struct nxge_param_map {
#if defined(_BIG_ENDIAN)
#else
#endif
typedef struct nxge_rcr_param {
#if defined(_BIG_ENDIAN)
#else
#endif
/*
* These are the properties of the TxDMA channels for this
* port (instance).
* <start> is the index of the first TDC that is being managed
* by this port.
* <count> is the number of TDCs being managed by this port.
* <owned> is the number of TDCs currently being utilized by this port.
*
* <owned> may be less than <count> in hybrid I/O systems.
*/
typedef struct {
} tdc_cfg_t;
/* Needs to have entries in the ndd table */
/*
* Hardware properties created by fcode.
* In order for those properties visible to the user
* command ndd, we need to add the following properties
* to the ndd defined parameter array and data structures.
*
* Use default static configuration for x86.
*/
typedef struct nxge_hw_pt_cfg {
/* Expand if we have more hardware or default configurations */
/* per port configuration */
typedef struct nxge_dma_pt_cfg {
/*
* Configuration for hardware initialization based on the
* hardware properties or the default properties.
*/
/* Transmit DMA channel: device wise */
/* Receive DMA channel */
/* Add more stuff later */
/* classification configuration */
typedef struct nxge_class_pt_cfg {
/* MAC table */
/* VLAN table */
/* class config value */
/* per Neptune sharable resources among ports */
typedef struct nxge_common {
/* DMA Channels: RDC and TDC */
/* Layer 2/3/4 */
/* FCRAM (hashing) */
/*
*/
typedef struct nxge_part_cfg {
/* Flow Classification Partition (flow partition select register) */
/* bits [19:15} in Hash 1. */
/* Add more here */
typedef struct nxge_usr_l3_cls {
typedef struct nxge_hw_list {
#if defined(sun4v)
/*
* With Hybrid I/O, a VR (virtualization region) is the moral
* equivalent of a device function as seen in the service domain.
* And, a guest domain can map up to 8 VRs for a single NIU for both
* of the physical ports. Hence, need space for up to the maximum
* number of VRs (functions) for the guest domain driver.
*
* For non-sun4v platforms, NXGE_MAX_PORTS provides the correct
* number of functions for the device. For sun4v platforms,
* NXGE_MAX_FUNCTIONS will be defined by the number of
* VRs that the guest domain can map.
*
* NOTE: This solution only works for one NIU and will need to
* revisit this for KT-NIU.
*/
#else
#endif
void *tcam;
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_COMMON_H */