/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
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*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_IB_ADAPTERS_TAVOR_CQ_H
#define _SYS_IB_ADAPTERS_TAVOR_CQ_H
/*
* Contains all of the prototypes, #defines, and structures necessary
* for the Completion Queue Processing routines.
* Specifically it contains the various completion types, flags,
* structures used for managing Tavor completion queues, and prototypes
* for many of the functions consumed by other parts of the Tavor driver
* (including those routines directly exposed through the IBTF CI
* interface).
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following defines specify the default number of Completion Queues (CQ)
* their maximum size. Settings exist for the supported DDR DIMM sizes of
* 128MB and 256MB. If a DIMM greater than 256 is found, then the 256MB
* profile is used. See tavor_cfg.c for more discussion on config profiles.
*
* For manual configuration (not using config profiles), these values are
* controllable through the "tavor_log_max_cq_sz" and "tavor_log_num_cq"
* configuration variables, respectively. To override config profile settings
* the 'tavor_alt_config_enable' configuration variable must first be set.
*
* Note: We also have a define for the minimum size of a CQ. CQs allocated
* with size 0, 1, 2, or 3 will always get back a CQ of size 4. This is the
* smallest size that Tavor hardware and software can correctly handle.
*/
/*
* Minimal configuration values.
*/
/*
* The following macro determines whether the contents of CQ memory (CQEs)
* need to be sync'd (with ddi_dma_sync()). This decision is based on whether
* the CQ memory is in DDR memory (no sync) or system memory (sync required).
* Note: It doesn't make much sense to put CQEs in DDR memory (since they are
* primarily written by HW and read by the CPU), but the driver does support
* that possibility. And it also supports the possibility that if a CQ in
* system memory is mapped DDI_DMA_CONSISTENT, it can be configured to not be
* sync'd because of the "sync override" parameter in the config profile.
*/
? 0 : 1)
/*
* The following defines specify the size of the individual Completion Queue
* Context (CQC) entries
*/
/*
* These are the defines for the Tavor CQ completion statuses. They are
* specified by the Tavor register specification.
*/
/*
* These are the defines for the Tavor CQ entry types. They are also
* specified by the Tavor register specification. They indicate what type
* of work request is completing (for successful completions). Note: The
* "SND" or "RCV" in each define is used to indicate whether the completion
* work request was from the Send work queue or the Receive work queue on
* the associated QP.
*/
/* Define for maximum CQ number mask (CQ number is 24 bits) */
/*
* This define and the following macro are used to find an event queue for a
* new CQ based on its completion queue number. Note: This is a rather
* simple method that we use today. We simply choose from one of the first
* 32 EQs based on the 5 least significant bits of the CQ number.
*/
/*
* The following macro is even simpler than the above one. This is used to
* find an event queue for CQ errors for a new CQ. In theory we could do this
* based on the CQ's number (as we do above). Today, however, all CQ error
* events go to one specific EQ (i.e. EQ #32).
*/
/*
* The following defines are used for Tavor CQ error handling. Note: For
* CQEs which correspond to error events, the Tavor device requires some
* special handling by software. These defines are used to identify and
* extract the necessary information from each error CQE, including status
* code (above), doorbell count, and whether a error completion is for a
* send or receive work request.
*/
#define TAVOR_CQ_SYNC_AND_DB 0
/* Defines for tracking whether a CQ is being used with special QP or not */
#define TAVOR_CQ_IS_NORMAL 0
/*
* The tavor_sw_cq_s structure is also referred to using the "tavor_cqhdl_t"
* typedef (see tavor_typedef.h). It encodes all the information necessary
* to track the various resources needed to allocate, initialize, poll, resize,
* and (later) free a completion queue (CQ).
*
* Specifically, it has a consumer index and a lock to ensure single threaded
* access to it. It has pointers to the various resources allocated for the
* completion queue, i.e. a CQC resource and the memory for the completion
* queue itself. It has flags to indicate whether the CQ requires
* ddi_dma_sync() ("cq_sync"). It also has a reference count and the number(s)
* of the EQs to which it is associated (for success and for errors).
*
* Additionally, it has a pointer to the associated MR handle (for the mapped
* queue memory) and a void pointer that holds the argument that should be
* passed back to the IBTF when events are generated on the CQ.
*
* We also have the always necessary backpointer to the resource for the
* CQ handle structure itself. But we also have pointers to the "Work Request
* ID" processing lists (both the lock and the regular list, as well as the
* head and tail for the "reapable" list). See tavor_wrid.c for more details.
*/
struct tavor_sw_cq_s {
void *cq_hdlrarg;
/* For Work Request ID processing */
};
#ifdef __cplusplus
}
#endif
#endif /* _SYS_IB_ADAPTERS_TAVOR_CQ_H */