qlge_hw.h revision bafec74292ca6805e5acb387856f4e60a5314b37
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 QLogic Corporation. All rights reserved.
*/
#ifndef _QLGE_HW_H
#define _QLGE_HW_H
#ifdef __cplusplus
extern "C" {
#endif
#define ISP_SCHULTZ 0x8000
#define MB_REG_COUNT 8
/*
* Data bit definitions.
*/
#define BIT_0 0x1
#define BIT_1 0x2
#define BIT_2 0x4
#define BIT_3 0x8
#define BIT_4 0x10
#define BIT_5 0x20
#define BIT_6 0x40
#define BIT_7 0x80
#define BIT_8 0x100
#define BIT_9 0x200
#define BIT_10 0x400
#define BIT_11 0x800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_16 0x10000
#define BIT_17 0x20000
#define BIT_18 0x40000
#define BIT_19 0x80000
#define BIT_20 0x100000
#define BIT_21 0x200000
#define BIT_22 0x400000
#define BIT_23 0x800000
#define BIT_24 0x1000000
#define BIT_25 0x2000000
#define BIT_26 0x4000000
#define BIT_27 0x8000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
typedef struct ql_stats
{
/* software statics */
/* TX */
/* RX */
/* statics by hw */
#define ETHERNET_CRC_SIZE 4
/*
* Register Definitions...
*/
#define MAILBOX_COUNT 16
/* System Register 0x00 */
#define PROC_ADDR_RDY BIT_31
#define PROC_ADDR_R BIT_30
#define PROC_ADDR_ERR BIT_29
#define PROC_ADDR_DA BIT_28
#define PROC_ADDR_FUNC0_MBI 0x00001180
#define PROC_ADDR_FUNC0_CTL 0x000011a1
#define PROC_ADDR_FUNC2_MBI 0x00001280
#define PROC_ADDR_FUNC2_CTL 0x000012a1
#define PROC_ADDR_MPI_RISC 0x00000000
#define PROC_ADDR_MDE 0x00010000
#define PROC_ADDR_REGBLOCK 0x00020000
#define PROC_ADDR_RISC_REG 0x00030000
/* System Register 0x08 */
#define SYSTEM_EFE_FAE 0x3u
enum {
SYS_EFE = (1 << 0),
SYS_OMP_DLY_MASK = 0x3f000000,
/*
* There are no values defined as of edit #15.
*/
};
/*
*/
#define RST_FO_TFO (1 << 0)
#define RST_FO_RR_MASK 0x00060000
#define RST_FO_RR_CQ_CAM 0x00000000
#define RST_FO_RR_DROP 0x00000001
#define RST_FO_RR_DQ 0x00000002
#define RST_FO_RR_RCV_FUNC_CQ 0x00000003
#define RST_FO_FRB BIT_12
#define RST_FO_MOP BIT_13
#define RST_FO_REG BIT_14
#define RST_FO_FR 0x8000u
/*
* Function Specific Control Register (FSC) bit definitions.
*/
enum {
FSC_DBRST_MASK = 0x00070000,
FSC_DBRST_256 = 0x00000000,
FSC_DBRST_512 = 0x00000001,
FSC_DBRST_768 = 0x00000002,
FSC_DBRST_1024 = 0x00000003,
FSC_DBL_MASK = 0x00180000,
FSC_DBL_DBRST = 0x00000000,
FSC_DBL_MAX_PLD = 0x00000008,
FSC_DBL_MAX_BRST = 0x00000010,
FSC_DBL_128_BYTES = 0x00000018,
FSC_EPC_MASK = 0x00c00000,
FSC_VM_PAGESIZE_MASK = 0x07000000,
FSC_VM_PAGE_2K = 0x00000100,
FSC_VM_PAGE_4K = 0x00000200,
FSC_VM_PAGE_8K = 0x00000300,
FSC_VM_PAGE_64K = 0x00000600,
};
/*
* Host Command Status Register (CSR) bit definitions.
*/
#define CSR_ERR_STS_MASK 0x0000003f
/*
* There are no valued defined as of edit #15.
*/
#define CSR_CMD_PARM_SHIFT 22
#define CSR_CMD_NOP 0x00000000
#define CSR_CMD_SET_RST 0x1000000
#define CSR_CMD_CLR_RST 0x20000000
#define CSR_CMD_SET_PAUSE 0x30000000
#define CSR_CMD_CLR_PAUSE 0x40000000
#define CSR_CMD_SET_H2R_INT 0x50000000
#define CSR_CMD_CLR_H2R_INT 0x60000000
#define CSR_CMD_PAR_EN 0x70000000
#define CSR_CMD_SET_BAD_PAR 0x80000000u
#define CSR_CMD_CLR_BAD_PAR 0x90000000u
#define CSR_CMD_CLR_R2PCI_INT 0xa0000000u
/*
* Configuration Register (CFG) bit definitions.
*/
enum {
CFG_LRQ = (1 << 0),
CFG_Q_SHIFT = 8,
CFG_Q_MASK = 0x7f000000
};
/*
* Status Register (STS) bit definitions.
*/
enum {
STS_FE = (1 << 0),
STS_FUNC_ID_MASK = 0x000000c0,
STS_FUNC_ID_SHIFT = 6,
};
/*
* Register (REV_ID) bit definitions.
*/
enum {
REV_ID_MASK = 0x0000000f,
REV_ID_NICROLL_SHIFT = 0,
REV_ID_NICREV_SHIFT = 4,
REV_ID_XGROLL_SHIFT = 8,
REV_ID_XGREV_SHIFT = 12,
REV_ID_CHIPREV_SHIFT = 28
};
/*
* Force ECC Error Register (FRC_ECC_ERR) bit definitions.
*/
enum {
FRC_ECC_PFE_SHIFT = 16,
};
/*
* Error Status Register (ERR_STS) bit definitions.
*/
enum {
ERR_STS_NOF = (1 << 0),
ERR_STS_LOC_SHIFT = 27
};
/*
* Semaphore Register (SEM) bit definitions.
*/
/*
* Example:
* reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
*/
#define SEM_CLEAR 0
#define SEM_SET 1
#define SEM_FORCE 3
#define SEM_XGMAC0_SHIFT 0
#define SEM_XGMAC1_SHIFT 2
#define SEM_ICB_SHIFT 4
#define SEM_MAC_ADDR_SHIFT 6
#define SEM_FLASH_SHIFT 8
#define SEM_PROBE_SHIFT 10
#define SEM_RT_IDX_SHIFT 12
#define SEM_PROC_REG_SHIFT 14
#define SEM_XGMAC0_MASK 0x00030000
#define SEM_XGMAC1_MASK 0x000c0000
#define SEM_ICB_MASK 0x00300000
#define SEM_MAC_ADDR_MASK 0x00c00000
#define SEM_FLASH_MASK 0x03000000
#define SEM_PROBE_MASK 0x0c000000
#define SEM_RT_IDX_MASK 0x30000000
#define SEM_PROC_REG_MASK 0xc0000000
/*
* Stop CQ Processing Register (CQ_STOP) bit definitions.
*/
enum {
CQ_STOP_QUEUE_MASK = (0x007f0000),
CQ_STOP_TYPE_MASK = (0x03000000),
CQ_STOP_TYPE_START = 0x00000100,
CQ_STOP_TYPE_STOP = 0x00000200,
CQ_STOP_TYPE_READ = 0x00000300,
};
/*
* MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
*/
#define MAC_ADDR_IDX_SHIFT 4
#define MAC_ADDR_TYPE_SHIFT 16
#define MAC_ADDR_TYPE_MASK 0x000f0000
#define MAC_ADDR_TYPE_CAM_MAC 0x00000000
#define MAC_ADDR_TYPE_MULTI_MAC 0x00010000
#define MAC_ADDR_TYPE_VLAN 0x00020000
#define MAC_ADDR_TYPE_MULTI_FLTR 0x00030000
#define MAC_ADDR_TYPE_FC_MAC 0x00040000
#define MAC_ADDR_TYPE_MGMT_MAC 0x00050000
#define MAC_ADDR_TYPE_MGMT_VLAN 0x00060000
#define MAC_ADDR_TYPE_MGMT_V4 0x00070000
#define MAC_ADDR_TYPE_MGMT_V6 0x00080000
#define MAC_ADDR_TYPE_MGMT_TU_DP 0x00090000
#define MAC_ADDR_ADR BIT_25
#define MAC_ADDR_RS BIT_26
#define MAC_ADDR_E BIT_27
#define MAC_ADDR_MR BIT_30
#define MAC_ADDR_MW BIT_31
#define MAX_MULTICAST_HW_SIZE 32
/*
* MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions.
*/
#define SPLT_HDR_EP BIT_31
/*
* NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
*/
enum {
NIC_RCV_CFG_PPE = (1 << 0),
NIC_RCV_CFG_VLAN_MASK = 0x00060000,
NIC_RCV_CFG_VLAN_ALL = 0x00000000,
NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
NIC_RCV_CFG_DFQ = 0 /* HARDCODE default queue to 0. */
};
/*
* Routing Index Register (RT_IDX) bit definitions.
*/
#define RT_IDX_IDX_SHIFT 8
#define RT_IDX_TYPE_MASK 0x000f0000
#define RT_IDX_TYPE_RT 0x00000000
#define RT_IDX_TYPE_RT_INV 0x00010000
#define RT_IDX_TYPE_NICQ 0x00020000
#define RT_IDX_TYPE_NICQ_INV 0x00030000
#define RT_IDX_DST_MASK 0x00700000
#define RT_IDX_DST_RSS 0x00000000
#define RT_IDX_DST_CAM_Q 0x00100000
#define RT_IDX_DST_COS_Q 0x00200000
#define RT_IDX_DST_DFLT_Q 0x00300000
#define RT_IDX_DST_DEST_Q 0x00400000
/* Nic Queue format - type 2 bits */
#define RT_IDX_BCAST 1
#define RT_IDX_MCAST BIT_1
#define RT_IDX_MCAST_MATCH BIT_2
#define RT_IDX_MCAST_REG_MATCH BIT_3
#define RT_IDX_MCAST_HASH_MATCH BIT_4
#define RT_IDX_FC_MACH BIT_5
#define RT_IDX_ETH_FCOE BIT_6
#define RT_IDX_CAM_HIT BIT_7
#define RT_IDX_CAM_BIT0 BIT_8
#define RT_IDX_CAM_BIT1 BIT_9
#define RT_IDX_VLAN_TAG BIT_10
#define RT_IDX_VLAN_MATCH BIT_11
#define RT_IDX_VLAN_FILTER BIT_12
#define RT_IDX_ETH_SKIP1 BIT_13
#define RT_IDX_ETH_SKIP2 BIT_14
#define RT_IDX_BCAST_MCAST_MATCH BIT_15
#define RT_IDX_802_3 BIT_16
#define RT_IDX_LLDP BIT_17
#define RT_IDX_UNUSED018 BIT_18
#define RT_IDX_UNUSED019 BIT_19
#define RT_IDX_UNUSED20 BIT_20
#define RT_IDX_UNUSED21 BIT_21
#define RT_IDX_ERR BIT_22
#define RT_IDX_VALID BIT_23
#define RT_IDX_TU_CSUM_ERR BIT_24
#define RT_IDX_IP_CSUM_ERR BIT_25
#define RT_IDX_MAC_ERR BIT_26
#define RT_IDX_RSS_TCP6 BIT_27
#define RT_IDX_RSS_TCP4 BIT_28
#define RT_IDX_RSS_IPV6 BIT_29
#define RT_IDX_RSS_IPV4 BIT_30
#define RT_IDX_RSS_MATCH BIT_31
/* Hierarchy for the NIC Queue Mask */
enum {
RT_IDX_ALL_ERR_SLOT = 0,
RT_IDX_MAC_ERR_SLOT = 0,
RT_IDX_BCAST_SLOT = 3,
RT_IDX_ALLMULTI_SLOT = 5,
RT_IDX_UNUSED6_SLOT = 6,
RT_IDX_UNUSED7_SLOT = 7,
RT_IDX_RSS_IPV4_SLOT = 8,
RT_IDX_RSS_IPV6_SLOT = 9,
RT_IDX_RSS_TCP4_SLOT = 10,
RT_IDX_RSS_TCP6_SLOT = 11,
RT_IDX_CAM_HIT_SLOT = 12,
RT_IDX_UNUSED013 = 13,
RT_IDX_UNUSED014 = 14,
RT_IDX_PROMISCUOUS_SLOT = 15,
RT_IDX_MAX_SLOTS = 16
};
enum {
CAM_OUT_ROUTE_FC = 0,
CAM_OUT_ROUTE_NIC = 1,
CAM_OUT_FUNC_SHIFT = 2,
};
#define FUNCTION_RESET 0x8000u
/* Function Specific Control Register 0x10 */
#define FSC_FE 0x8000
/* Configuration Register 0x28 */
#define LOAD_LCQ 0x40
#define LOAD_ICB_ERR 0x20
#define LOAD_LRQ 0x01
#define FN0_NET 0
#define FN1_NET 1
#define FN0_FC 2
#define FN1_FC 3
/*
* Semaphore Register (SEM) bit definitions.
*/
#define SEM_CLEAR 0
#define SEM_SET 1
#define SEM_FORCE 3
#define SEM_XGMAC0_SHIFT 0
#define SEM_XGMAC1_SHIFT 2
#define SEM_ICB_SHIFT 4
#define SEM_MAC_ADDR_SHIFT 6
#define SEM_FLASH_SHIFT 8
#define SEM_PROBE_SHIFT 10
#define SEM_RT_IDX_SHIFT 12
#define SEM_PROC_REG_SHIFT 14
#define SEM_XGMAC0_MASK 0x00030000
#define SEM_XGMAC1_MASK 0x000c0000
#define SEM_ICB_MASK 0x00300000
#define SEM_MAC_ADDR_MASK 0x00c00000
#define SEM_FLASH_MASK 0x03000000
#define SEM_PROBE_MASK 0x0c000000
#define SEM_RT_IDX_MASK 0x30000000
#define SEM_PROC_REG_MASK 0xc0000000
/* System Register 0x08 */
#define SYSTEM_EFE_FAE 0x3u
/* Interrupt Status Register-1 0x3C */
#define CQ_0_NOT_EMPTY BIT_0
#define CQ_1_NOT_EMPTY BIT_1
#define CQ_2_NOT_EMPTY BIT_2
#define CQ_3_NOT_EMPTY BIT_3
#define CQ_4_NOT_EMPTY BIT_4
#define CQ_5_NOT_EMPTY BIT_5
#define CQ_6_NOT_EMPTY BIT_6
#define CQ_7_NOT_EMPTY BIT_7
#define CQ_8_NOT_EMPTY BIT_8
#define CQ_9_NOT_EMPTY BIT_9
#define CQ_10_NOT_EMPTY BIT_10
#define CQ_11_NOT_EMPTY BIT_11
#define CQ_12_NOT_EMPTY BIT_12
#define CQ_13_NOT_EMPTY BIT_13
#define CQ_14_NOT_EMPTY BIT_14
#define CQ_15_NOT_EMPTY BIT_15
#define CQ_16_NOT_EMPTY BIT_16
/* Processor Address Register 0x00 */
#define HOST_CMD_SET_RISC_RESET 0x10000000u
#define HOST_CMD_CLEAR_RISC_RESET 0x20000000u
#define HOST_CMD_SET_RISC_PAUSE 0x30000000u
#define HOST_CMD_RELEASE_RISC_PAUSE 0x40000000u
#define HOST_CMD_SET_RISC_INTR 0x50000000u
#define HOST_CMD_CLEAR_RISC_INTR 0x60000000u
#define HOST_CMD_SET_PARITY_ENABLE 0x70000000u
#define HOST_CMD_FORCE_BAD_PARITY 0x80000000u
#define HOST_CMD_RELEASE_BAD_PARITY 0x90000000u
#define HOST_CMD_CLEAR_RISC_TO_HOST_INTR 0xA0000000u
#define HOST_TO_MPI_INTR_NOT_DONE 0x200
#define RISC_RESET BIT_8
#define RISC_PAUSED BIT_10
/* Semaphor Register 0x64 */
#define QL_SEM_BITS_BASE_CODE 0x1u
#define QL_PORT0_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE)
#define QL_SEM_MASK_BASE_CODE 0x30000u
#define QL_PORT0_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE)
/* XGMAC Address Register 0x78 */
/* XGMAC Register Set */
#define REG_XGMAC_GLOBAL_CONFIGURATION 0x108
#define GLOBAL_CONFIG_JUMBO_MODE 0x40
#define REG_XGMAC_MAC_TX_CONFIGURATION 0x10C
#define XGMAC_MAC_TX_ENABLE 0x02
#define REG_XGMAC_MAC_RX_CONFIGURATION 0x110
#define XGMAC_MAC_RX_ENABLE 0x02
#define REG_XGMAC_FLOW_CONTROL 0x11C
#define REG_XGMAC_MAC_TX_PARAM 0x134
#define REG_XGMAC_MAC_RX_PARAM 0x138
#define REG_XGMAC_MAC_TX_PKTS 0x200
#define REG_XGMAC_MAC_TX_OCTETS 0x208
#define REG_XGMAC_MAC_TX_MULTCAST_PKTS 0x210
#define REG_XGMAC_MAC_TX_BROADCAST_PKTS 0x218
#define REG_XGMAC_MAC_TX_PAUSE_PKTS 0x230
#define REG_XGMAC_MAC_RX_OCTETS 0x300
#define REG_XGMAC_MAC_RX_OCTETS_OK 0x308
#define REG_XGMAC_MAC_RX_PKTS 0x310
#define REG_XGMAC_MAC_RX_PKTS_OK 0x318
#define REG_XGMAC_MAC_RX_BROADCAST_PKTS 0x320
#define REG_XGMAC_MAC_RX_MULTCAST_PKTS 0x328
#define REG_XGMAC_MAC_RX_JABBER_PKTS 0x348
#define REG_XGMAC_MAC_FCS_ERR 0x360
#define REG_XGMAC_MAC_ALIGN_ERR 0x368
#define REG_XGMAC_MAC_RX_SYM_ERR 0x370
#define REG_XGMAC_MAC_RX_INT_ERR 0x378
#define REG_XGMAC_MAC_RX_PAUSE_PKTS 0x388
#define REG_XGMAC_MAC_PHY_ADDR 0x430
#define REG_XGMAC_MAC_RX_FIFO_DROPS 0x5B8
/* MAC Protocol Address Index Register Set 0xA8 */
#define MAC_PROTOCOL_TYPE_CAM_MAC (0x0)
#define MAC_PROTOCOL_TYPE_MULTICAST (0x10000u)
/* NIC Receive Configuration Register 0xD4 */
#define RECV_CONFIG_DEFAULT_Q_MASK (0x7F000000u)
#define RECV_CONFIG_VTAG_REMOVAL_MASK (0x80000u)
#define RECV_CONFIG_VTAG_RV 0x08
/*
* 10G MAC Address Register (XGMAC_ADDR) bit definitions.
*/
#define PAUSE_SRC_LO 0x00000100
#define PAUSE_SRC_HI 0x00000104
#define GLOBAL_CFG 0x00000108
#define GLOBAL_CFG_RESET (1 << 0)
#define TX_CFG 0x0000010c
#define TX_CFG_RESET (1 << 0)
#define RX_CFG 0x00000110
#define RX_CFG_RESET (1 << 0)
#define FLOW_CTL 0x0000011c
#define PAUSE_OPCODE 0x00000120
#define PAUSE_TIMER 0x00000124
#define PAUSE_FRM_DEST_LO 0x00000128
#define PAUSE_FRM_DEST_HI 0x0000012c
#define MAC_TX_PARAMS 0x00000134
#define MAC_TX_PARAMS_SIZE_SHIFT 16
#define MAC_RX_PARAMS 0x00000138
#define MAC_SYS_INT 0x00000144
#define MAC_SYS_INT_MASK 0x00000148
#define MAC_MGMT_INT 0x0000014c
#define MAC_MGMT_IN_MASK 0x00000150
#define EXT_ARB_MODE 0x000001fc
#define TX_PKTS 0x00000200
#define TX_PKTS_LO 0x00000204
#define TX_BYTES 0x00000208
#define TX_BYTES_LO 0x0000020C
#define TX_MCAST_PKTS 0x00000210
#define TX_MCAST_PKTS_LO 0x00000214
#define TX_BCAST_PKTS 0x00000218
#define TX_BCAST_PKTS_LO 0x0000021C
#define TX_UCAST_PKTS 0x00000220
#define TX_UCAST_PKTS_LO 0x00000224
#define TX_CTL_PKTS 0x00000228
#define TX_CTL_PKTS_LO 0x0000022c
#define TX_PAUSE_PKTS 0x00000230
#define TX_PAUSE_PKTS_LO 0x00000234
#define TX_64_PKT 0x00000238
#define TX_64_PKT_LO 0x0000023c
#define TX_65_TO_127_PKT 0x00000240
#define TX_65_TO_127_PKT_LO 0x00000244
#define TX_128_TO_255_PKT 0x00000248
#define TX_128_TO_255_PKT_LO 0x0000024c
#define TX_256_511_PKT 0x00000250
#define TX_256_511_PKT_LO 0x00000254
#define TX_512_TO_1023_PKT 0x00000258
#define TX_512_TO_1023_PKT_LO 0x0000025c
#define TX_1024_TO_1518_PKT 0x00000260
#define TX_1024_TO_1518_PKT_LO 0x00000264
#define TX_1519_TO_MAX_PKT 0x00000268
#define TX_1519_TO_MAX_PKT_LO 0x0000026c
#define TX_UNDERSIZE_PKT 0x00000270
#define TX_UNDERSIZE_PKT_LO 0x00000274
#define TX_OVERSIZE_PKT 0x00000278
#define TX_OVERSIZE_PKT_LO 0x0000027c
#define RX_HALF_FULL_DET 0x000002a0
#define TX_HALF_FULL_DET_LO 0x000002a4
#define RX_OVERFLOW_DET 0x000002a8
#define TX_OVERFLOW_DET_LO 0x000002ac
#define RX_HALF_FULL_MASK 0x000002b0
#define TX_HALF_FULL_MASK_LO 0x000002b4
#define RX_OVERFLOW_MASK 0x000002b8
#define TX_OVERFLOW_MASK_LO 0x000002bc
#define STAT_CNT_CTL 0x000002c0
#define AUX_RX_HALF_FULL_DET 0x000002d0
#define AUX_TX_HALF_FULL_DET 0x000002d4
#define AUX_RX_OVERFLOW_DET 0x000002d8
#define AUX_TX_OVERFLOW_DET 0x000002dc
#define AUX_RX_HALF_FULL_MASK 0x000002f0
#define AUX_TX_HALF_FULL_MASK 0x000002f4
#define AUX_RX_OVERFLOW_MASK 0x000002f8
#define AUX_TX_OVERFLOW_MASK 0x000002fc
#define RX_BYTES 0x00000300
#define RX_BYTES_LO 0x00000304
#define RX_BYTES_OK 0x00000308
#define RX_BYTES_OK_LO 0x0000030c
#define RX_PKTS 0x00000310
#define RX_PKTS_LO 0x00000314
#define RX_PKTS_OK 0x00000318
#define RX_PKTS_OK_LO 0x0000031c
#define RX_BCAST_PKTS 0x00000320
#define RX_BCAST_PKTS_LO 0x00000324
#define RX_MCAST_PKTS 0x00000328
#define RX_MCAST_PKTS_LO 0x0000032c
#define RX_UCAST_PKTS 0x00000330
#define RX_UCAST_PKTS_LO 0x00000334
#define RX_UNDERSIZE_PKTS 0x00000338
#define RX_UNDERSIZE_PKTS_LO 0x0000033c
#define RX_OVERSIZE_PKTS 0x00000340
#define RX_OVERSIZE_PKTS_LO 0x00000344
#define RX_JABBER_PKTS 0x00000348
#define RX_JABBER_PKTS_LO 0x0000034c
#define RX_UNDERSIZE_FCERR_PKTS 0x00000350
#define RX_UNDERSIZE_FCERR_PKTS_LO 0x00000354
#define RX_DROP_EVENTS 0x00000358
#define RX_DROP_EVENTS_LO 0x0000035c
#define RX_FCERR_PKTS 0x00000360
#define RX_FCERR_PKTS_LO 0x00000364
#define RX_ALIGN_ERR 0x00000368
#define RX_ALIGN_ERR_LO 0x0000036c
#define RX_SYMBOL_ERR 0x00000370
#define RX_SYMBOL_ERR_LO 0x00000374
#define RX_MAC_ERR 0x00000378
#define RX_MAC_ERR_LO 0x0000037c
#define RX_CTL_PKTS 0x00000380
#define RX_CTL_PKTS_LO 0x00000384
#define RX_PAUSE_PKTS 0x00000388
#define RX_PAUSE_PKTS_LO 0x0000038c
#define RX_64_PKTS 0x00000390
#define RX_64_PKTS_LO 0x00000394
#define RX_65_TO_127_PKTS 0x00000398
#define RX_65_TO_127_PKTS_LO 0x0000039c
#define RX_128_255_PKTS 0x000003a0
#define RX_128_255_PKTS_LO 0x000003a4
#define RX_256_511_PKTS 0x000003a8
#define RX_256_511_PKTS_LO 0x000003ac
#define RX_512_TO_1023_PKTS 0x000003b0
#define RX_512_TO_1023_PKTS_LO 0x000003b4
#define RX_1024_TO_1518_PKTS 0x000003b8
#define RX_1024_TO_1518_PKTS_LO 0x000003bc
#define RX_1519_TO_MAX_PKTS 0x000003c0
#define RX_1519_TO_MAX_PKTS_LO 0x000003c4
#define RX_LEN_ERR_PKTS 0x000003c8
#define RX_LEN_ERR_PKTS_LO 0x000003cc
#define MDIO_TX_DATA 0x00000400
#define MDIO_RX_DATA 0x00000410
#define MDIO_CMD 0x00000420
#define MDIO_PHY_ADDR 0x00000430
#define MDIO_PORT 0x00000440
#define MDIO_STATUS 0x00000450
#define TX_CBFC_PAUSE_FRAMES0 0x00000500
#define TX_CBFC_PAUSE_FRAMES0_LO 0x00000504
#define TX_CBFC_PAUSE_FRAMES1 0x00000508
#define TX_CBFC_PAUSE_FRAMES1_LO 0x0000050C
#define TX_CBFC_PAUSE_FRAMES2 0x00000510
#define TX_CBFC_PAUSE_FRAMES2_LO 0x00000514
#define TX_CBFC_PAUSE_FRAMES3 0x00000518
#define TX_CBFC_PAUSE_FRAMES3_LO 0x0000051C
#define TX_CBFC_PAUSE_FRAMES4 0x00000520
#define TX_CBFC_PAUSE_FRAMES4_LO 0x00000524
#define TX_CBFC_PAUSE_FRAMES5 0x00000528
#define TX_CBFC_PAUSE_FRAMES5_LO 0x0000052C
#define TX_CBFC_PAUSE_FRAMES6 0x00000530
#define TX_CBFC_PAUSE_FRAMES6_LO 0x00000534
#define TX_CBFC_PAUSE_FRAMES7 0x00000538
#define TX_CBFC_PAUSE_FRAMES7_LO 0x0000053C
#define TX_FCOE_PKTS 0x00000540
#define TX_FCOE_PKTS_LO 0x00000544
#define TX_MGMT_PKTS 0x00000548
#define TX_MGMT_PKTS_LO 0x0000054C
#define RX_CBFC_PAUSE_FRAMES0 0x00000568
#define RX_CBFC_PAUSE_FRAMES0_LO 0x0000056C
#define RX_CBFC_PAUSE_FRAMES1 0x00000570
#define RX_CBFC_PAUSE_FRAMES1_LO 0x00000574
#define RX_CBFC_PAUSE_FRAMES2 0x00000578
#define RX_CBFC_PAUSE_FRAMES2_LO 0x0000057C
#define RX_CBFC_PAUSE_FRAMES3 0x00000580
#define RX_CBFC_PAUSE_FRAMES3_LO 0x00000584
#define RX_CBFC_PAUSE_FRAMES4 0x00000588
#define RX_CBFC_PAUSE_FRAMES4_LO 0x0000058C
#define RX_CBFC_PAUSE_FRAMES5 0x00000590
#define RX_CBFC_PAUSE_FRAMES5_LO 0x00000594
#define RX_CBFC_PAUSE_FRAMES6 0x00000598
#define RX_CBFC_PAUSE_FRAMES6_LO 0x0000059C
#define RX_CBFC_PAUSE_FRAMES7 0x000005A0
#define RX_CBFC_PAUSE_FRAMES7_LO 0x000005A4
#define RX_FCOE_PKTS 0x000005A8
#define RX_FCOE_PKTS_LO 0x000005AC
#define RX_MGMT_PKTS 0x000005B0
#define RX_MGMT_PKTS_LO 0x000005B4
#define RX_NIC_FIFO_DROP 0x000005B8
#define RX_NIC_FIFO_DROP_LO 0x000005BC
#define RX_FCOE_FIFO_DROP 0x000005C0
#define RX_FCOE_FIFO_DROP_LO 0x000005C4
#define RX_MGMT_FIFO_DROP 0x000005C8
#define RX_MGMT_FIFO_DROP_LO 0x000005CC
#define RX_PKTS_PRIORITY0 0x00000600
#define RX_PKTS_PRIORITY0_LO 0x00000604
#define RX_PKTS_PRIORITY1 0x00000608
#define RX_PKTS_PRIORITY1_LO 0x0000060C
#define RX_PKTS_PRIORITY2 0x00000610
#define RX_PKTS_PRIORITY2_LO 0x00000614
#define RX_PKTS_PRIORITY3 0x00000618
#define RX_PKTS_PRIORITY3_LO 0x0000061C
#define RX_PKTS_PRIORITY4 0x00000620
#define RX_PKTS_PRIORITY4_LO 0x00000624
#define RX_PKTS_PRIORITY5 0x00000628
#define RX_PKTS_PRIORITY5_LO 0x0000062C
#define RX_PKTS_PRIORITY6 0x00000630
#define RX_PKTS_PRIORITY6_LO 0x00000634
#define RX_PKTS_PRIORITY7 0x00000638
#define RX_PKTS_PRIORITY7_LO 0x0000063C
#define RX_OCTETS_PRIORITY0 0x00000640
#define RX_OCTETS_PRIORITY0_LO 0x00000644
#define RX_OCTETS_PRIORITY1 0x00000648
#define RX_OCTETS_PRIORITY1_LO 0x0000064C
#define RX_OCTETS_PRIORITY2 0x00000650
#define RX_OCTETS_PRIORITY2_LO 0x00000654
#define RX_OCTETS_PRIORITY3 0x00000658
#define RX_OCTETS_PRIORITY3_LO 0x0000065C
#define RX_OCTETS_PRIORITY4 0x00000660
#define RX_OCTETS_PRIORITY4_LO 0x00000664
#define RX_OCTETS_PRIORITY5 0x00000668
#define RX_OCTETS_PRIORITY5_LO 0x0000066C
#define RX_OCTETS_PRIORITY6 0x00000670
#define RX_OCTETS_PRIORITY6_LO 0x00000674
#define RX_OCTETS_PRIORITY7 0x00000678
#define RX_OCTETS_PRIORITY7_LO 0x0000067C
#define TX_PKTS_PRIORITY0 0x00000680
#define TX_PKTS_PRIORITY0_LO 0x00000684
#define TX_PKTS_PRIORITY1 0x00000688
#define TX_PKTS_PRIORITY1_LO 0x0000068C
#define TX_PKTS_PRIORITY2 0x00000690
#define TX_PKTS_PRIORITY2_LO 0x00000694
#define TX_PKTS_PRIORITY3 0x00000698
#define TX_PKTS_PRIORITY3_LO 0x0000069C
#define TX_PKTS_PRIORITY4 0x000006A0
#define TX_PKTS_PRIORITY4_LO 0x000006A4
#define TX_PKTS_PRIORITY5 0x000006A8
#define TX_PKTS_PRIORITY5_LO 0x000006AC
#define TX_PKTS_PRIORITY6 0x000006B0
#define TX_PKTS_PRIORITY6_LO 0x000006B4
#define TX_PKTS_PRIORITY7 0x000006B8
#define TX_PKTS_PRIORITY7_LO 0x000006BC
#define TX_OCTETS_PRIORITY0 0x000006C0
#define TX_OCTETS_PRIORITY0_LO 0x000006C4
#define TX_OCTETS_PRIORITY1 0x000006C8
#define TX_OCTETS_PRIORITY1_LO 0x000006CC
#define TX_OCTETS_PRIORITY2 0x000006D0
#define TX_OCTETS_PRIORITY2_LO 0x000006D4
#define TX_OCTETS_PRIORITY3 0x000006D8
#define TX_OCTETS_PRIORITY3_LO 0x000006DC
#define TX_OCTETS_PRIORITY4 0x000006E0
#define TX_OCTETS_PRIORITY4_LO 0x000006E4
#define TX_OCTETS_PRIORITY5 0x000006E8
#define TX_OCTETS_PRIORITY5_LO 0x000006EC
#define TX_OCTETS_PRIORITY6 0x000006F0
#define TX_OCTETS_PRIORITY6_LO 0x000006F4
#define TX_OCTETS_PRIORITY7 0x000006F8
#define TX_OCTETS_PRIORITY7_LO 0x000006FC
#define RX_DISCARD_PRIORITY0 0x00000700
#define RX_DISCARD_PRIORITY0_LO 0x00000704
#define RX_DISCARD_PRIORITY1 0x00000708
#define RX_DISCARD_PRIORITY1_LO 0x0000070C
#define RX_DISCARD_PRIORITY2 0x00000710
#define RX_DISCARD_PRIORITY2_LO 0x00000714
#define RX_DISCARD_PRIORITY3 0x00000718
#define RX_DISCARD_PRIORITY3_LO 0x0000071C
#define RX_DISCARD_PRIORITY4 0x00000720
#define RX_DISCARD_PRIORITY4_LO 0x00000724
#define RX_DISCARD_PRIORITY5 0x00000728
#define RX_DISCARD_PRIORITY5_LO 0x0000072C
#define RX_DISCARD_PRIORITY6 0x00000730
#define RX_DISCARD_PRIORITY6_LO 0x00000734
#define RX_DISCARD_PRIORITY7 0x00000738
#define RX_DISCARD_PRIORITY7_LO 0x0000073C
#define CQ0_ID 0x0
#define NIC_CORE 0x1
/* Routing Index Register 0xE4 */
#define ROUTING_INDEX_MW BIT_31
#define ROUTING_INDEX_DEFAULT_ENABLE_MASK (0x8320000u)
#define ROUTING_INDEX_DEFAULT_DISABLE_MASK (0x0320000u)
/* Routing Data Register 0xE8 */
#define ROUTE_AS_CAM_HIT 0x80
#define ROUTE_AS_BCAST_MCAST_MATCH 0x8000u
enum {
};
#define ROUTING_MASK_INDEX_MAX 16
/*
* General definitions...
*/
/*
* Below are a number compiler switches for controlling driver behavior.
* Some are not supported under certain conditions and are notated as such.
*/
/* MTU & Frame Size stuff */
#define JUMBO_MTU 9000
#define JUMBO_FRAME_SIZE 9600
#define VLAN_ID_LEN 2
#define NUM_RX_RING_ENTRIES (2048)
#define NUM_SMALL_BUFFERS (2048)
#define NUM_LARGE_BUFFERS (2048)
/ VM_PAGE_SIZE) + 1) + \
(((NUM_LARGE_BUFFERS * sizeof (uint64_t)) \
/ VM_PAGE_SIZE) + 1))
#define MAX_CQ 128
/* coalescing */
/* coalescing */
#define UDELAY_COUNT 3
#define UDELAY_DELAY 10
#define MAX_RX_RINGS 128
#define MAX_TX_RINGS 16
/*
* Large & Small Buffers for Receives
*/
struct lrg_buf_q_entry {
#define IAL_LAST_ENTRY 0x00000001
#define IAL_CONT_ENTRY 0x00000002
#define IAL_FLAG_MASK 0x00000003
};
struct bufq_addr_element {
};
#define QL_NO_RESET 0
#define QL_DO_RESET 1
/* Link must be in one of these states */
enum link_state_t {
};
/* qlge->flags definitions. */
#define QL_LINK_OPTICAL BIT_12
#define QL_MSI_ENABLED BIT_13
#define INTERRUPTS_ENABLED BIT_14
#define ADAPTER_SUSPENDED BIT_15
#define QLA_PM_CAPABLE BIT_16
/*
* ISP PCI Configuration Register Set structure definitions.
*/
typedef volatile struct
{
volatile uint8_t prog_class;
volatile uint8_t base_class;
volatile uint8_t cache_line_size;
volatile uint8_t latency_timer;
volatile uint8_t header_type;
volatile uint32_t io_base_address;
volatile uint32_t pci_doorbell_mem_base_address_lower;
volatile uint32_t pci_doorbell_mem_base_address_upper;
volatile uint16_t sub_vendor_id;
volatile uint16_t sub_device_id;
volatile uint32_t expansion_rom;
volatile uint8_t max_latency;
volatile uint16_t pcie_device_control;
volatile uint16_t link_status;
volatile uint16_t msi_msg_control;
volatile uint16_t msi_x_msg_control;
} pci_cfg_t;
/*
*
* Schultz Control Registers Index
*
*/
#define REG_PROCESSOR_ADDR 0x00
#define REG_PROCESSOR_DATA 0x04
#define REG_SYSTEM 0x08
#define REG_RESET_FAILOVER 0x0C
#define REG_FUNCTION_SPECIFIC_CONTROL 0x10
#define REG_HOST_CMD_STATUS 0x14
#define REG_ICB_RID 0x1C
#define REG_ICB_ACCESS_ADDRESS_LOWER 0x20
#define REG_ICB_ACCESS_ADDRESS_UPPER 0x24
#define REG_CONFIGURATION 0x28
#define INTR_EN_INTR_MASK 0x007f0000
#define INTR_EN_TYPE_MASK 0x03000000
#define INTR_EN_TYPE_ENABLE 0x00000100
#define INTR_EN_TYPE_DISABLE 0x00000200
#define INTR_EN_TYPE_READ 0x00000300
#define INTR_EN_IHD 0x00002000
#define INTR_EN_EI 0x00004000
#define INTR_EN_EN 0x00008000
#define REG_STATUS 0x30
#define REG_INTERRUPT_ENABLE 0x34
#define REG_INTERRUPT_MASK 0x38
#define REG_INTERRUPT_STATUS_1 0x3C
#define REG_ERROR_STATUS 0x54
#define REG_SEMAPHORE 0x64
#define REG_XGMAC_ADDRESS 0x78
#define REG_XGMAC_DATA 0x7C
#define REG_NIC_ENHANCED_TX_SCHEDULE 0x80
#define REG_CNA_ENHANCED_TX_SCHEDULE 0x84
#define REG_FLASH_ADDRESS 0x88
#define REG_FLASH_DATA 0x8C
#define REG_STOP_CQ_PROCESSING 0x90
#define REG_PAGE_TABLE_RID 0x94
#define REG_WQ_PAGE_TABLE_BASE_ADDR_LOWER 0x98
#define REG_WQ_PAGE_TABLE_BASE_ADDR_UPPER 0x9C
#define REG_CQ_PAGE_TABLE_BASE_ADDR_LOWER 0xA0
#define REG_CQ_PAGE_TABLE_BASE_ADDR_UPPER 0xA4
#define REG_MAC_PROTOCOL_ADDRESS_INDEX 0xA8
#define REG_MAC_PROTOCOL_DATA 0xAC
#define REG_SPLIT_HEADER 0xC0
#define REG_NIC_RECEIVE_CONFIGURATION 0xD4
#define REG_MGMT_RCV_CFG 0xE0
#define REG_ROUTING_INDEX 0xE4
#define REG_ROUTING_DATA 0xE8
#define REG_RSVD7 0xEC
#define REG_XG_SERDES_ADDR 0xF0
#define REG_XG_SERDES_DATA 0xF4
#define REG_PRB_MX_ADDR 0xF8
#define REG_PRB_MX_DATA 0xFC
#define INTR_MASK_PI 0x00000001
#define INTR_MASK_HL0 0x00000002
#define INTR_MASK_LH0 0x00000004
#define INTR_MASK_HL1 0x00000008
#define INTR_MASK_LH1 0x00000010
#define INTR_MASK_SE 0x00000020
#define INTR_MASK_LSC 0x00000040
#define INTR_MASK_MC 0x00000080
/* Interrupt Enable Register 0x34 */
#define INTR_ENABLED 0x8000
#define GLOBAL_ENABLE_INTR 0x4000
#define ENABLE_MSI_MULTI_INTR 0x2000
#define ONE_INTR_MASK 0x3FF0000u
#define ENABLE_INTR 0x0100
#define DISABLE_INTR 0x0200
#define VERIFY_INTR_ENABLED 0x0300
(ONE_INTR_MASK | ENABLE_INTR))
#define ISP_ENABLE_GLOBAL_INTRS(qlge) { \
(0x40000000u | GLOBAL_ENABLE_INTR)); \
}
#define ISP_DISABLE_GLOBAL_INTRS(qlge) { \
REG_INTERRUPT_ENABLE, (0x40000000u)); \
}
#define REQ_Q_VALID 0x10
#define RSP_Q_VALID 0x10
/*
* Mailbox Registers
*/
#define MPI_REG 0x1002
#define NUM_MAILBOX_REGS 16
#define FUNC_0_IN_MAILBOX_0_REG_OFFSET 0x1180
#define FUNC_0_OUT_MAILBOX_0_REG_OFFSET 0x1190
#define FUNC_1_IN_MAILBOX_0_REG_OFFSET 0x1280
#define FUNC_1_OUT_MAILBOX_0_REG_OFFSET 0x1290
/*
* Control Register Set definitions.
*/
typedef volatile struct
{
} dev_reg_t;
typedef volatile struct
{
/*
* DMA registers read only
*/
typedef volatile struct
{
#define DMAREGS_SIZE (sizeof (iop_dmaregs_t))
#ifdef QL_DEBUG
typedef struct crash_record {
#endif
/*
* I/O register access macros
* #if QL_DEBUG & 1
*/
/*
* QLGE-specific ioctls ...
*/
/*
* Definition of ioctls commands
*/
#define QLA_IOCTL_CMD_FIRST QLA_PCI_STATUS
#define QLA_IOCTL_CMD_LAST QLA_SOFT_RESET
/* Solaris IOCTL can copy in&out up to 1024 bytes each time */
#define IOCTL_BUFFER_SIZE 1024
typedef struct ioctl_header_info {
#define IOCTL_HEADER_LEN sizeof (ioctl_header_info_t)
struct ql_pci_reg {
};
struct ql_device_reg {
};
struct ql_flash_io_info {
};
struct qlnic_mpi_version_info {
};
struct qlnic_link_status_info {
};
struct qlnic_prop_info {
};
typedef struct ql_adapter_info {
struct ether_addr cur_addr;
typedef struct ql_dump_header {
typedef struct ql_dump_image_header {
#define DUMP_TYPE_CORE_DUMP 1
#define DUMP_TYPE_REGISTER_DUMP 2
#define DUMP_TYPE_DRIVER_DUMP 3
/* utility request */
#define DUMP_REQUEST_CORE BIT_1
#define DUMP_REQUEST_REGISTER BIT_2
#define DUMP_REQUEST_DRIVER BIT_3
#define DUMP_REQUEST_ALL BIT_7
typedef struct ql_dump_footer {
/*
* Solaris qlnic exit status.
*/
#define QN_ERR_BASE 0x30000000
#define FLT_REGION_FDT 0x1A
#define ISP_8100_FDT_ADDR 0x360000
#define ISP_8100_FDT_SIZE 0x80
#define FLT_REGION_FLT 0x1C
#define ISP_8100_FLT_ADDR 0x361000
#define ISP_8100_FLT_SIZE 0x1000
#define FLT_REGION_NIC_BOOT_CODE 0x2E
#define ISP_8100_NIC_BOOT_CODE_ADDR 0x0
#define ISP_8100_NIC_BOOT_CODE_SIZE 0x80000
#define FLT_REGION_MPI_FW_USE 0x42
#define ISP_8100_MPI_FW_USE_ADDR 0xF0000
#define ISP_8100_MPI_FW_USE_SIZE 0x10000
#define FLT_REGION_MPI_RISC_FW 0x40
#define ISP_8100_MPI_RISC_FW_ADDR 0x100000
#define ISP_8100_MPI_RISC_FW_SIZE 0x10000
#define FLT_REGION_VPD0 0x2C
#define ISP_8100_VPD0_ADDR 0x140000
#define ISP_8100_VPD0_SIZE 0x200
#define FLT_REGION_NIC_PARAM0 0x46
#define ISP_8100_NIC_PARAM0_ADDR 0x140200
#define ISP_8100_NIC_PARAM0_SIZE 0x200
#define FLT_REGION_VPD1 0x2D
#define ISP_8100_VPD1_ADDR 0x140400
#define ISP_8100_VPD1_SIZE 0x200
#define FLT_REGION_NIC_PARAM1 0x47
#define ISP_8100_NIC_PARAM1_ADDR 0x140600
#define ISP_8100_NIC_PARAM1_SIZE 0x200
#define FLT_REGION_MPI_CFG 0x41
#define ISP_8100_MPI_CFG_ADDR 0x150000
#define ISP_8100_MPI_CFG_SIZE 0x10000
#define FLT_REGION_EDC_PHY_FW 0x45
#define ISP_8100_EDC_PHY_FW_ADDR 0x170000
#define ISP_8100_EDC_PHY_FW_SIZE 0x20000
#define FLT_REGION_FC_BOOT_CODE 0x07
#define ISP_8100_FC_BOOT_CODE_ADDR 0x200000
#define ISP_8100_FC_BOOT_CODE_SIZE 0x80000
#define FLT_REGION_FC_FW 0x01
#define ISP_8100_FC_FW_ADDR 0x280000
#define ISP_8100_FC_FW_SIZE 0x80000
#define FLT_REGION_FC_VPD0 0x14
#define ISP_8100_FC_VPD0_ADDR 0x340000
#define ISP_8100_FC_VPD0_SIZE 0x200
#define FLT_REGION_FC_NVRAM0 0x15
#define ISP_8100_FC_NVRAM0_ADDR 0x340200
#define ISP_8100_FC_NVRAM0_SIZE 0x200
#define FLT_REGION_FC_VPD1 0x16
#define ISP_8100_FC_VPD1_ADDR 0x340400
#define ISP_8100_FC_VPD1_SIZE 0x200
#define FLT_REGION_FC_NVRAM1 0x17
#define ISP_8100_FC_NVRAM1_ADDR 0x340600
#define ISP_8100_FC_NVRAM1_SIZE 0x200
#define FLT_REGION_FC_BOOT_CODE 0x07
#define ISP_8100_FC_BOOT_CODE_ADDR 0x200000
#define ISP_8100_FC_BOOT_CODE_SIZE 0x80000
#define FLT_REGION_FC_FW 0x01
#define ISP_8100_FC_FW_ADDR 0x280000
#define ISP_8100_FC_FW_SIZE 0x80000
#define FLT_REGION_TIME_STAMP 0x60
/* flash region for testing */
#define FLT_REGION_WIN_FW_DUMP0 0x48
#define ISP_8100_WIN_FW_DUMP0_ADDR 0x190000
#define ISP_8100_WIN_FW_DUMP0_SIZE 0x30000
#define ISP_8100_FLASH_TEST_REGION_SIZE 0x10000
/* mailbox */
#define QL_8XXX_SFP_SIZE 256
/*
* ISP mailbox commands from Host
*/
#define MBC_NO_OPERATION 0 /* No Operation. */
#define MBC_INIT_RISC_RAM 0xE
#define IDC_REQ_DEST_FUNC_1_MASK BIT_1
#define IDC_REQ_DEST_FUNC_2_MASK BIT_2
#define IDC_REQ_DEST_FUNC_3_MASK BIT_3
enum IDC_REQ_DEST_FUNC {
IDC_REQ_DEST_FUNC_ALL = 0x0F
};
#define IDC_REQ_TIMEOUT_MASK 0x01
#define MBC_SET_WAKE_ON_LANE_MODE 0x110
#define MBC_SET_WAKE_ON_LANE_FILTER 0x111
#define MBC_CLEAR_WAKE_ON_LANE_FILTER 0x112
#define MBC_SET_WAKE_ON_LANE_MAGIC_PKT 0x113
#define MBC_CLEAR_WAKE_ON_LANE_MAGIC_PKT 0x114
#define MBC_PORT_RESET 0x120
#define MBC_SET_PORT_CONFIG 0x122
#define MBC_GET_PORT_CONFIG 0x123
#define ENABLE_JUMBO_FRAME_SIZE_MASK BIT_16
#define MBC_GET_LINK_STATUS 0x124
#define MBC_SET_LED_CONFIG 0x125
#define MBC_GET_LED_CONFIG 0x126
/*
* ISP mailbox command complete status codes
*/
#define MBS_COMMAND_COMPLETE 0x4000
#define MBS_INVALID_COMMAND 0x4001
#define MBS_HOST_INTERFACE_ERROR 0x4002
#define MBS_TEST_FAILED 0x4003
#define MBS_POST_ERROR 0x4004
#define MBS_COMMAND_ERROR 0x4005
#define MBS_COMMAND_PARAMETER_ERROR 0x4006
#define MBS_PORT_ID_USED 0x4007
#define MBS_LOOP_ID_USED 0x4008
#define MBS_ALL_IDS_IN_USE 0x4009
#define MBS_NOT_LOGGED_IN 0x400A
#define MBS_LOOP_DOWN 0x400B
#define MBS_LOOP_BACK_ERROR 0x400C
#define MBS_CHECKSUM_ERROR 0x4010
/* Async Event Status */
#define MBA_IDC_INTERMEDIATE_COMPLETE 0x1000
#define MBA_SYSTEM_ERR 0x8002
#define MBA_LINK_UP 0x8011
enum {
};
#define MBA_LINK_DOWN 0x8012
#define MBA_IDC_COMPLETE 0x8100
#define MBA_IDC_REQUEST_NOTIFICATION 0x8101
#define MBA_IDC_TIME_EXTENDED 0x8102
#define MBA_DCBX_CONFIG_CHANGE 0x8110
#define MBA_NOTIFICATION_LOST 0x8120
#define MBA_SFT_TRANSCEIVER_INSERTION 0x8130
#define MBA_SFT_TRANSCEIVER_REMOVAL 0x8131
#define MBA_FIRMWARE_INIT_COMPLETE 0x8400
#define MBA_FIRMWARE_INIT_FAILED 0x8401
typedef struct firmware_version_info {
typedef struct phy_firmware_version_info {
#define ENABLE_JUMBO BIT_16
#define STD_PAUSE 0x20
#define PP_PAUSE 0x40
#define LOOP_INTERNAL_PARALLEL 0x02
#define LOOP_INTERNAL_SERIAL 0x04
#define LOOP_EXTERNAL_PHY 0x06
typedef struct port_cfg_info {
enum {
PAUSE_MODE_STANDARD, /* Standard Ethernet Pause */
PAUSE_MODE_PER_PRIORITY /* Class Based Pause */
};
/* Mailbox command parameter structure definition. */
typedef struct mbx_cmd {
} mbx_cmd_t;
/* Returned Mailbox registers. */
typedef struct mbx_data {
} mbx_data_t;
#define MPI_CORE_REGS_ADDR 0x00030000
#define MPI_CORE_REGS_CNT 127
#define MPI_CORE_SH_REGS_CNT 16
#define TEST_REGS_ADDR 0x00001000
#define TEST_REGS_CNT 23
#define RMII_REGS_ADDR 0x00001040
#define RMII_REGS_CNT 64
#define FCMAC1_REGS_ADDR 0x00001080
#define FCMAC2_REGS_ADDR 0x000010c0
#define FCMAC_REGS_CNT 64
#define FC1_MBX_REGS_ADDR 0x00001100
#define FC2_MBX_REGS_ADDR 0x00001240
#define FC_MBX_REGS_CNT 64
#define IDE_REGS_ADDR 0x00001140
#define IDE_REGS_CNT 64
#define NIC1_MBX_REGS_ADDR 0x00001180
#define NIC2_MBX_REGS_ADDR 0x00001280
#define NIC_MBX_REGS_CNT 64
#define SMBUS_REGS_ADDR 0x00001200
#define SMBUS_REGS_CNT 64
#define I2C_REGS_ADDR 0x00001fc0
#define I2C_REGS_CNT 64
#define MEMC_REGS_ADDR 0x00003000
#define MEMC_REGS_CNT 256
#define PBUS_REGS_ADDR 0x00007c00
#define PBUS_REGS_CNT 256
#define MDE_REGS_ADDR 0x00010000
#define MDE_REGS_CNT 6
#define CODE_RAM_ADDR 0x00020000
#define CODE_RAM_CNT 0x2000
#define MEMC_RAM_ADDR 0x00100000
#define MEMC_RAM_CNT 0x2000
/* 64 probes, 8 bytes per probe + 4 bytes to list the probe ID */
#define NUMBER_OF_PROBES 34
#define NUMBER_ROUTING_REG_ENTRIES 48
#define WORDS_PER_ROUTING_REG_ENTRY 4
(4096 * 1) + (4 * 2) + (8 * 2) + \
(16 * 1) + (4 * 1) + (4 * 4) + \
(4 * 1))
/* Save both the address and data register */
#define WORDS_PER_MAC_PROT_ENTRY 2
#define MPI_COREDUMP_COOKIE 0x5555aaaa
typedef struct mpi_coredump_global_header {
char id_string[16];
char driver_info[0xE0];
typedef struct mpi_coredump_segment_header {
char description[16];
typedef struct ql_mpi_coredump {
/* one interrupt state for each CQ */
#define XGMAC_REGISTER_END 0x740
#define XG_SERDES_ADDR_RDY BIT_31
#define XG_SERDES_ADDR_R BIT_30
#define CORE_SEG_NUM 1
#define TEST_LOGIC_SEG_NUM 2
#define RMII_SEG_NUM 3
#define FCMAC1_SEG_NUM 4
#define FCMAC2_SEG_NUM 5
#define FC1_MBOX_SEG_NUM 6
#define IDE_SEG_NUM 7
#define NIC1_MBOX_SEG_NUM 8
#define SMBUS_SEG_NUM 9
#define FC2_MBOX_SEG_NUM 10
#define NIC2_MBOX_SEG_NUM 11
#define I2C_SEG_NUM 12
#define MEMC_SEG_NUM 13
#define PBUS_SEG_NUM 14
#define MDE_SEG_NUM 15
#define NIC1_CONTROL_SEG_NUM 16
#define NIC2_CONTROL_SEG_NUM 17
#define NIC1_XGMAC_SEG_NUM 18
#define NIC2_XGMAC_SEG_NUM 19
#define WCS_RAM_SEG_NUM 20
#define MEMC_RAM_SEG_NUM 21
#define XAUI_AN_SEG_NUM 22
#define XAUI_HSS_PCS_SEG_NUM 23
#define XFI_AN_SEG_NUM 24
#define XFI_TRAIN_SEG_NUM 25
#define XFI_HSS_PCS_SEG_NUM 26
#define XFI_HSS_TX_SEG_NUM 27
#define XFI_HSS_RX_SEG_NUM 28
#define XFI_HSS_PLL_SEG_NUM 29
#define INTR_STATES_SEG_NUM 31
#define ETS_SEG_NUM 34
#define PROBE_DUMP_SEG_NUM 35
#define ROUTING_INDEX_SEG_NUM 36
#define MAC_PROTOCOL_SEG_NUM 37
/* Force byte packing for the following structures */
#pragma pack(1)
/*
* Work Queue (Request Queue) Initialization Control Block (WQICB)
*/
struct wqicb_t {
#define Q_LEN_CPP_CONT 0x0000
#define Q_LEN_CPP_16 0x0001
#define Q_LEN_CPP_32 0x0002
#define Q_LEN_CPP_64 0x0003
#define Q_LEN_CPP_512 0x0006
#define Q_PRI_SHIFT 1
#define Q_FLAGS_LC 0x1000
#define Q_FLAGS_LB 0x2000
#define Q_FLAGS_LI 0x4000
#define Q_FLAGS_LO 0x8000
#define Q_CQ_ID_RSS_RV 0x8000
};
/*
* Completion Queue (Response Queue) Initialization Control Block (CQICB)
*/
struct cqicb_t {
#define FLAGS_LV 0x08
#define FLAGS_LS 0x10
#define FLAGS_LL 0x20
#define FLAGS_LI 0x40
#define FLAGS_LC 0x80
#define LEN_CPP_CONT 0x0000
#define LEN_CPP_32 0x0001
#define LEN_CPP_64 0x0002
#define LEN_CPP_128 0x0003
/* producer index host shadow */
};
struct ricb {
#define RSS_L4K 0x80
#define RSS_L6K 0x01
#define RSS_LI 0x02
#define RSS_LB 0x04
#define RSS_LM 0x08
#define RSS_RI4 0x10
#define RSS_RT4 0x20
#define RSS_RI6 0x40
#define RSS_RT6 0x80
#define RSS_HASH_CQ_ID_MAX 1024
};
/*
* Host Command IOCB Formats
*/
#define OPCODE_OB_MAC_IOCB 0x01
#define OPCODE_OB_MAC_OFFLOAD_IOCB 0x02
#define OPCODE_IB_MAC_IOCB 0x20
#define OPCODE_IB_SYS_EVENT_IOCB 0x3f
/*
* The following constants define control bits for buffer
* length fields for all IOCB's.
*/
struct oal_entry {
};
/* 32 words, 128 bytes */
struct ob_mac_iocb_req {
#define OB_MAC_IOCB_REQ_IPv6 0x80
#define OB_MAC_IOCB_REQ_IPv4 0x40
};
/* 16 words, 64 bytes */
struct ob_mac_iocb_rsp {
#define OB_MAC_IOCB_RSP_B 0x80
};
#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
struct ib_mac_iocb_rsp {
#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
#define IB_MAC_IOCB_RSP_VLAN_ID_MASK 0xFFF
#define IB_MAC_IOCB_RSP_HV 0x20
#define IB_MAC_IOCB_RSP_HS 0x40
#define IB_MAC_IOCB_RSP_HL 0x80
};
/* 16 words, 64 bytes */
struct ib_sys_event_iocb_rsp {
};
#define SYS_EVENT_PORT_LINK_UP 0x0
#define SYS_EVENT_PORT_LINK_DOWN 0x1
#define SYS_EVENT_MULTIPLE_CAM_HITS 0x6
#define SYS_EVENT_SOFT_ECC_ERR 0x7
#define SYS_EVENT_MAC_INTERRUPT 0x9
#define SYS_EVENT_PCI_ERR_READING_SML_LRG_BUF 0x40
/*
* Status Register (#define STATUS) bit definitions.
*/
#define STATUS_FE (1 << 0)
#define STATUS_FUNC_ID_MASK 0x000000c0
#define STATUS_FUNC_ID_SHIFT 6
/*
* Generic Response Queue IOCB Format which abstracts the difference between
* IB_MAC, OB_MAC IOCBs
*/
struct net_rsp_iocb {
};
/* Restore original packing rules */
#pragma pack()
#define RESPONSE_ENTRY_SIZE (sizeof (struct net_rsp_iocb))
#define REQUEST_ENTRY_SIZE (sizeof (struct ob_mac_iocb_req))
/* flash */
/* Little endian machine correction defines. */
#ifdef _LITTLE_ENDIAN
#define LITTLE_ENDIAN_16(x)
#define LITTLE_ENDIAN_24(x)
#define LITTLE_ENDIAN_32(x)
#define LITTLE_ENDIAN_64(x)
#endif /* _LITTLE_ENDIAN */
/* Big endian machine correction defines. */
#ifdef _BIG_ENDIAN
#define BIG_ENDIAN_16(x)
#define BIG_ENDIAN_24(x)
#define BIG_ENDIAN_32(x)
#define BIG_ENDIAN_64(x)
#endif /* _BIG_ENDIAN */
/* Flash Address Register 0x88 */
#define FLASH_RDY_FLAG BIT_31
#define FLASH_R_FLAG BIT_30
#define FLASH_ERR_FLAG BIT_29
#define FLASH_CONF_ADDR 0x7D0000u
#define FLASH_ADDR_MASK 0x7F0000
#define FLASH_WRSR_CMD 0x01
#define FLASH_PP_CMD 0x02
#define FLASH_READ_CMD 0x03
#define FLASH_WRDI_CMD 0x04
#define FLASH_RDSR_CMD 0x05
#define FLASH_WREN_CMD 0x06
#define FLASH_RDID_CMD 0x9F
#define FLASH_RES_CMD 0xAB
/*
* Flash definitions.
*/
typedef struct ql_flash_info {
/*
* Flash Description Table
*/
#define FLASH_DESC_VERSION 1
typedef struct flash_desc {
} flash_desc_t;
/* flash manufacturer id's */
/* flash id defines */
/* flash type defines */
#define FLASH_PAGE BIT_31
typedef struct {
} pci_header_t;
typedef struct {
} pci_data_t;
#define PCI_HEADER0 0x55
#define PCI_HEADER1 0xAA
#define PCI_DATASIG "PCIR"
#define PCI_SECTOR_SIZE 0x200
#define PCI_CODE_X86PC 0
#define PCI_CODE_FCODE 1
#define PCI_CODE_HPPA 2
#define PCI_CODE_EFI 3
#define PCI_CODE_FW 0xfe
#define PCI_IND_LAST_IMAGE 0x80
#define SBUS_CODE_FCODE 0xf1
#define FBUFSIZE 100
/* Flash Layout Table Data Structure(FLTDS) */
typedef struct ql_fltds {
} ql_fltds_t;
/* Image Layout Table Data Structure(ILTDS) */
typedef struct ql_iltds_header {
#define IMAGE_TABLE_HEADER_LEN sizeof (ql_iltds_header_t)
#define ILTDS_REGION_VERSION_LEN_NA 0 /* version not applicable */
typedef struct ql_iltds_img_entry {
#define ILTDS_IMG_SWAP_NONE 0 /* no swap needed */
#define ILTDS_IMG_SWAP_WORD 1
#define ILTDS_IMG_CARD_TYPE_ALL 0 /* apply to all types */
#define IMAGE_TABLE_ENTRY_LEN sizeof (ql_iltds_img_entry_t)
typedef struct ql_iltds_time_stamp {
#define IMAGE_TABLE_TIME_STAMP_LEN sizeof (ql_iltds_time_stamp_t)
#define IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES 5
typedef struct ql_iltds_description_header {
#define ILTDS_DESCRIPTION_HEADERS_LEN sizeof (ql_iltds_description_header_t)
/* flash layout table definition */
/* header */
typedef struct ql_flt_header {
/* table entry */
typedef struct ql_flt_entry {
#define FLT_ATTR_READ_ONLY BIT_0
#define FLT_ATTR_NEED_FW_RESTART BIT_1
#define FLT_ATTR_NEED_DATA_REALOAD BIT_2
/* flt table */
typedef struct ql_flt {
} ql_flt_t;
/* Nic Configuration Table */
enum {
};
typedef struct ql_nic_config {
#ifdef __cplusplus
}
#endif
#endif /* _QLGE_HW_H */